Multi-state EEPROM having write-verify control circuit

ABSTRACT

An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 5,570,315. The reissue applications that have beenfiled for the reissue of U.S. Pat. No. 5,570,315 include parent reissueapplication Ser. No. 09/134,897 filed on Aug. 17, 1998, and this reissueapplication Ser. No. 11/451,587, which is a division of this parentreissue application. In addition, reissue application Ser. No.11/451,584; Ser. No. 11/451,585; Ser. No. 11/451,586; Ser. No.11/451,588; Ser. No. 11/451,589; Ser. No. 11/451,590; Ser. No.11/451,591; Ser. No. 11/451,592; and Ser. No. 11/451,593 have been filedas additional division reissue applications of the above-noted parentreissue application so as to be consistent with the RestrictionRequirement mailed in the above-noted parent reissue application on Apr.20, 2006.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electrically programmablenonvolatile semiconductor memory device (EEPROM) and, more particularly,to an EEPROM for performing a multivalue storing operation for storinginformation of two or more bits in one memory cell.

2. Description of the Related Art

As one of EEPROMs, a NAND EEPROM which can be integrated at a highdensity is known. In this NAND EEPROM, a plurality of memory cells areconnected in series with each other as one unit such that adjacentmemory cells have a source and a drain in common, and these memory cellsare connected to a bit line. A memory cell generally has an FETMOSstructure in which a charge accumulation layer and a control gate arestacked. A memory cell array is integrated and formed in a p-type wellformed in a p- or n-type substrate. The drain side of a NAND cell isconnected to a bit line through a selection gate, and the source side isconnected to a common source line through a selection gate. The controlgates of memory cells are continuously arranged in a row direction toform a word line.

The operation of this NAND-cell EEPROM is as follows. A data writeoperation is sequentially performed from a memory cell at a positionfarthest from the bit line. A high voltage Vpp (=about 20 V) is appliedto the control gate of a selected memory cell, an intermediate voltageVppm (=about 10 V) is applied to the control gate and selection gate ofa memory cell closer to the bit line than the selected memory cell, anda voltage of 0 V or an intermediate voltage Vm (=about 8 V) is appliedto the bit line in accordance with data. When the voltage is 0 V isapplied to the bit line, the potential of the bit line is transferred tothe drain of the selected memory cell, and electrons are injected intothe charge accumulation layer of the selected memory cell. In this case,the threshold voltage of the selected memory cell is positively shifted.This state is represented by, e.g., “1”. When the voltage Vm is appliedto the bit line, electrons are not effectively injected into the chargeaccumulation layer of the selected memory cell, and, therefore, thethreshold voltage of the selected memory cell is kept negative withoutbeing changed. This state is an erased state, and is represented by “0”.A data write operation is performed to memory cells which share acontrol gate at once.

A data erase operation is performed to all the memory cells in a NANDcell at once. More specifically, all the control gates are set to be 0V, and the p-type well is set to be 20 V. At this time, the selectiongate, the bit line, and the source line are set to be 20 V. In thismanner, electrons are discharged from the charge accumulation layers ofall the memory cells into the p-type well, and the threshold voltages ofthe memory cells are negatively shifted.

A data read operation is performed as follows. That is, the control gateof a selected memory cell is set to be 0 V, the control gates andselection gates of the remaining memory cells are set to be a powersupply potential Vcc (e.g., 5 V), and it is detected whether a currentflows in the selected memory cell. Due to restrictions of the readoperation, a threshold voltage set upon a “1”-data write operation mustbe controlled to fall within a range of 0 V to Vcc. For this purpose, awrite verify operation is performed to detect only a memory cell inwhich data “1” is not sufficiently written, and rewritten data is setsuch that a rewrite operation is performed to only the memory cell inwhich data “1” is not sufficiently written (bit-by-bit verifyoperation). The memory cell in which data “1” is not sufficientlywritten is detected by performing a read operation (verify readoperation) such that a selected control gate is set to be, e.g., 0.5 V(verify voltage).

More specifically, when the threshold voltage of the memory cell has amargin with respect to 0 V and is not set to be 0.5 V or more, a currentflows in the selected memory cell, and the selected memory cell isdetected as a memory cell in which data “1” is not sufficiently written.Since a current flows in a memory cell set to be a “0”-data-writtenstate, a circuit called a verify circuit for compensating the currentflowing in the memory cell is arranged to prevent the memory cell frombeing erroneously recognized as a memory cell in which data “1” is notsufficiently written. This verify circuit executes a write verifyoperation at a high speed. When a data write operation is performedwhile a write operation and a write verify operation are repeated, awrite time for each memory cell is made optimum, and the thresholdvoltage of each memory cell set upon a “1”-data write operation iscontrolled to fall within a range of 0 V to Vcc.

In this NAND-cell EEPROM, in order to realize a multivalue storingoperation, for example, it is considered that states set upon a writeoperation are set to be three states represented by “0”, “1”, and “2”. A“0”-data-written state is defined as a state wherein the thresholdvoltage is negative, a “1”-data-written state is defined as a statewherein the threshold voltage ranges from 0 V to ½ Vcc, and a“2”-data-written state is defined as a state wherein the thresholdvoltage ranges from ½ Vcc to Vcc. In a conventional verify circuit, amemory cell set to be a “0”-data written state can be prevented frombeing erroneously recognized as a memory cell in which data “1” or “2”is not sufficiently written.

However, the conventional verify circuit is not designed for amultivalue storing operation. For this reason, assuming that a memorycell set to be a data “2”-written state has a threshold voltage equal toor higher than a verify voltage for detecting whether data “1” is notsufficiently written and equal to or lower than ½ Vcc, when it is to bedetected whether data “1” is not sufficiently written, no current flowsin the memory cell, and the memory cell is erroneously recognized as amemory cell in which data “2” is sufficiently written.

In addition, in order to prevent erroneous recognition of a memory cellin which data is not sufficiently written and to perform a multivaluewrite verify operation, a verify write operation is performed to set amemory cell, in which data “1” is sufficiently written, in a“2”-data-written state, by detecting whether the memory cell is a memorycell in which data “2” is not sufficiently written. However, in thiscase, a memory cell set to be a “2”-data-written state is set in a“1”-data-written state at first and is then set in a “2”-data-writtenstate. For this reason, a longer time is required for the writeoperation, and the write operation cannot be performed at a high speed.

As described above, when a conventional NAND-cell EEPROM is used forperforming a multivalue storing operation, and a bit-by-bit verifyoperation is performed by a conventional verify circuit, an erroneousverify operation is disadvantageously performed.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an EEPROM capable ofstoring multivalue information and performing a write verify operationat high speed without causing an erroneous verify operation.

According to a first aspect of the present invention, there is provideda nonvolatile semiconductor memory device capable of storing multivaluedata, characterized by comprising a memory cell array in which memorycells which can be electrically programmed and each of which has atleast three storage states are arranged in a matrix, a plurality ofwrite data circuits for temporarily storing data for controlling writeoperation states of the plurality of memory cells in the memory cellarray, write means for simultaneously performing a write operation tothe plurality of memory cells in accordance with contents of the datacircuits respectively corresponding to the plurality of memory cells,verify means for simultaneously checking states of the plurality ofmemory cells set upon the write operation, and means for updating thecontents of the write data circuits such that a rewrite operation isperformed to only a memory cell, in which data is not sufficientlywritten, on the basis of the contents of the data circuits and thestates of the memory cells set upon the write operation, wherein thewrite operation based on the contents of the data circuits, a writeverify operation, and an operation for updating the contents of thewrite data circuits are repeatedly performed until the plurality ofmemory cells are set in predetermined written states, therebyelectrically performing a data write operation.

According to a second aspect of the present invention, there is provideda nonvolatile semiconductor memory device having a memory cell arrayconstituted by a plurality of memory cells which are arranged in amatrix and each of which can be electrically programmed, each of thememory cells having arbitrary data “i” (i=0, 1, . . . , n−1: n≧3) as atleast three storage states, and a storage state corresponding to data“0” being an erasure state, characterized by comprising a plurality ofdata circuits each serving as a sense amplifier and having a function ofstoring sensed information as data for controlling a write operationstate of a corresponding memory cell, write means for simultaneouslyperforming a write operation to the plurality of memory cells inaccordance with contents of the data circuits respectively correspondingto the plurality of memory cells, ith (i=1, 2, . . . , n−1) write verifymeans for simultaneously checking whether the storage state of each ofthe plurality of memory cells set upon the write operation becomes astorage state of data “i”, ith (i=1, . . . , n−1) data circuit contentsimultaneous updating means for simultaneously updating the contents ofdata circuits corresponding to a memory cell in which data “i” is to bestored, such that a rewrite operation is performed to only a memorycell, in which data is not sufficiently written, on the basis of thecontents of the data circuits and the storage states of the memory cellsafter the write operation, and data circuit content updating means forperforming a storage checking operation performed by the ith writeverify means and a simultaneous updating operation performed by the ithdata circuit content simultaneous updating means, from data “1” to data“n−1”n−1 times so as to update the contents of all the plurality of datacircuits, wherein the ith data circuit content simultaneous updatingmeans, of bit line potentials at which the storage states of the memorycells set upon a write operation are output by the ith write verifymeans, a bit line potential corresponding to a memory cell in which data“i” (i≧1) is to be stored is sensed/stored as rewrite data, and for bitlines corresponding to memory cells in which data except for data “i”are to be stored the bit line potential at which the state of the memorycell set upon the write operation is output is corrected in accordancewith the contents of the data circuits so as to sense/store to hold thecontents of data circuit, holding the data storage states of the datacircuits until the bit line potentials are corrected, operating the datacircuits as sense amplifiers while the corrected bit line potentials areheld, and simultaneously updating the contents of the data circuitcorresponding to the memory cell in which data “i” is to be stored, anda write operation and a data circuit content updating operation based onthe contents of the data circuits are repeatedly performed until thememory cells are set in predetermined written states, therebyelectrically performing a data write operation.

Preferred embodiments of the present invention will be described below.

-   (1) The data circuits control write operation states of the memory    cells in accordance with data stored in the data circuits in a write    operation to perform control such that the states of the memory    cells are changed into predetermined written states or the states of    the memory cells are held in states set prior to the write    operation.-   (2) For a data circuit corresponding to a memory cell to be set in    an “i”-data-written state, an ith data circuit content simultaneous    updating means changes data of the data circuit into data for    controlling the state of the memory cell to hold the state of the    memory cell in a state set prior to the write operation when memory    cells corresponding to a data circuit in which data for changing a    memory cell into an “i”-data-written state is stored reach an    “i”-data-written state, sets data for controlling the state of the    memory cell to change the state of the memory cell into the    “i”-data-written state in the data circuit when the memory cell    corresponding to the data circuit in which data for changing a    memory cell into an “i”-data-written state is stored does not reach    the “i”-data-written state, and sets data for controlling the state    of the memory cell to hold the state of the memory cell set prior to    the write operation when the data circuit stores data for    controlling the state of the memory cell to hold the state of the    memory cell in the state set prior to the write operation, and the    ith data circuit content simultaneous updating means does not change    contents of the data circuits corresponding to the memory cells in    which data except for data “i” are to be stored.-   (3) Each of the memory cells is constituted by stacking and forming    a charge accumulation layer and a control gate on a semiconductor    layer and stores arbitrary data “i” (i=0, 1, . . . , n−1; n≧3) as at    least three storage states and as multivalue data using magnitudes    of threshold voltages, and the ith write verify means applies a    predetermined ith verify potential to the control gate to verify    whether a threshold voltage of a memory cell set to the    “i”-data-written state is a desired threshold voltage.-   (4) A storage state corresponding to data “0” is an erased state, a    difference between the threshold voltage corresponding to the data    “n−1” state and the threshold voltage corresponding to a data “0”    state is a maximum, and threshold voltages corresponding to data    “1”, “2”, . . . , “i”, . . . , “n−2” states range from the threshold    voltage corresponding to the data “0” state to the threshold voltage    corresponding to the data “n−1” state, and the threshold voltages    corresponding to the data “1”, “2”, . . . , “i”, . . . , “n−2”    states are ordered from the threshold voltage corresponding to the    data “0” state. The nonvolatile semiconductor memory device    comprises a first bit line potential setting circuit for, of a    plurality of bit line potentials at which states of memory cells set    upon a write operation are output by the ith write verify means,    when the data circuits sense a bit line potential corresponding to a    data circuit whose contents are data for controlling the states of    the memory cells to hold the states of the memory cells in states    set prior to the write operation, setting the bit line potential to    be a first correction bit line potential which becomes data for    controlling the states of the memory cells to hold states of the    memory cells in states set prior to the write operation, and a jth    bit line potential setting circuit for, of bit line potentials    corresponding to memory cells set to be data “j”-written states    (i+1≦j) among bit line potentials at which states of the memory    cells set upon a write operation are output by the ith (1≦i≦n−2)    write verify means, when a data circuit senses only a bit line    potential corresponding to a data circuit whose contents are data    for controlling states of memory cells to set the states of the    memory cells to data “j”-written states, setting the bit line    potential in a second correction bit line potential which becomes    data for controlling the states of the memory cells to change the    states of the memory cells into the data “j”-written states,    wherein, to update the contents of the data circuits, a bit line    potential at which states of the memory cells set upon a write    operation are output by an ith write verify operation is corrected    by the first, (i+1)th, (i+2)th, . . . , (n−1)th bit line potential    setting circuits.-   (5) Each of the data circuits is constituted by a first data storage    unit for storing information indicating whether a state of a memory    cell is held in a state set prior to a write operation and a second    data storage unit for, when the information of the first data    storage unit is not information for controlling the state of the    memory cell to hold the state of the memory cell in a state set    prior to the write operation, storing information indicating a    written state “i” (i=1, 2, . . . , n−1) to be stored in the memory    cell, the first data storage unit having a function of    sensing/storing bit line potentials which are corrected by the    first, (i+1)th, (i+2)th , . . . , (n−1)th bit line potential setting    circuits in accordance with the contents of the data circuits to    perform the data circuit content updating operation and at which the    storage states of the memory cells set upon the write operation are    output by the ith write verify operation.-   (6) The nonvolatile semiconductor memory device comprises a write    prevention bit line voltage output circuit for, when the information    of the first data storage unit is information for controlling the    state of the memory cells to hold the state of the memory cells in    states set prior to a write operation, outputting a write prevention    bit line voltage to a bit line in the write operation, and an ith    (i=1, 2, . . . , n−1) bit line voltage output circuit for, when the    information of the first data storage unit is not information for    controlling the states of the memory cells to hold the states of the    memory cells in the states set prior to the write operation,    outputting a bit line voltage in an ith write operation in    accordance with information indicating a written state “i” to be    stored in a memory cell of the second data storage unit.-   (7) The first bit line potential setting circuit and the write    prevention bit line voltage output circuit are common first bit line    voltage control circuits. The input voltage of each of the common    first bit line voltage control circuits has an input voltage whose    output is to be a write prevention bit line voltage in a write    operation and a first correction bit line potential in a data    circuit content updating operation. The jth (j=2, 3, . . . , n−1)    bit line potential setting circuit and the jth write bit line    voltage output circuit are common jth bit line voltage control    circuits. Each of the common jth bit line voltage control circuits    has an input whose output is to be a jth write bit line voltage in    the write operation and a second correction bit line potential in a    data circuit content updating operation.-   (8) Each of the memory cells is constituted by stacking and forming    a charge accumulation layer and a control gate on a semiconductor    layer, and the memory cells are connected in series with each other    as units each constituted by a plurality of memory cells to form    NAND-cell structures.-   (9) Each of the memory cells is constituted by stacking and forming    a charge accumulation layer and a control gate on a semiconductor    layer, thereby forming a NOR-cell structure.

A multivalue (n-value) storage type EEPROM according to the first andsecond aspects of the present invention is constituted such that averify read operation is performed through n−1 basic operation cycles.An erased state is represented by data “0”, and multivalue levels arerepresented by “0”, “1”, . . . , “i”, . . . , “n−1” in an order from asmall threshold voltage. In this case, an ith cycle is constituted toverify whether an “i”-data write operation is sufficiently performed.For this reason, the EEPROM comprises a verify potential generationcircuit for applying a predetermined verify voltage at an level in theith cycle such that a current flows in a memory cell having a selectedcontrol gate when an “i”-data write operation is sufficiently performed,and a sense amplifier for detecting a bit line voltage to determinewhether a write operation is sufficiently performed. In the ith cycle,the bit line of a memory cell in which data “0”, . . . , “i−1” arewritten has a first verify circuit such that the current of the memorycell is compensated for when it is detected that the data aresufficiently written in the memory cell and the current of the memorycell is not compensated for when it is detected that the data are notsufficiently written in the memory cell. In the ith cycle, for the bitline of a memory cell in which data “i+1”, . . . , “n−1” are written,the current of the memory cell is compensated for by the first verifycircuit when it is detected that the data are sufficiently written inthe memory cell in advance and a second verify circuit for setting a bitline voltage is installed such that the current of the memory cell flowswhen it is detected that the data are not sufficiently written in thememory cell.

The EEPROM comprises a first data storage unit for storing dataindicating whether data is sufficiently written and a second datastorage unit for storing whether a multivalue level to be written is anyone of data “1”, . . . , “n−1”. The first data storage unit also has thefunction of a sense amplifier for detecting whether data is sufficientlywritten. In addition, the EEPROM is characterized by comprising a bitline write voltage output circuit for outputting a bit line voltage in awrite operation in accordance with a desired written state such that,when there is memory cell which does not reach a predetermined writtenstate, a rewrite operation is performed to only this memory cell.

According to the present invention, after a multivalue data writeoperation is performed, it is detected whether the written states ofmemory cells reach their desired multivalue level states. When there isa memory cell which does not reach its desired multivalue level state, abit line voltage in a write operation is output in accordance with adesired written state such that a rewrite operation is performed to onlythis memory cell. The write operation and the verify read operation arerepeated, and a data write operation is ended when all the memory cellsreach their desired written states, respectively.

As described above, according to the present invention, a time forperforming one write cycle is shortened, and a write operation isrepeated many times within a short time while the degree of progress ofa written state is checked, so that the range of the threshold voltagedistribution of a memory cell in which a data write operation is finallyended can be narrowed at a high speed.

According to a third aspect of the present invention, a bit linepotential in a read operation is controlled to exhibit the thresholdvoltage of a memory cell. A common source line is set to be 6 V, avoltage of 2 V is applied to a selected control gate, and the potentialof the common source line is transferred to the bit line. When the bitline potential reaches a certain value, a current flowing in the memorycell is stopped, and the bit line potential is given as a value obtainedby subtracting the threshold voltage of the memory cell from the controlgate voltage of 2 V. When the bit line potential is 3 V, the thresholdvoltage of the memory cell is −1 V. A non-selected control gate and aselection gate are set to be 6 V such that the bit line potential is notdetermined by the potential of the non-selected memory cell or aselection transistor.

An erased state is represented by data “0”, multivalue levels arerepresented by “0”, “1”, . . . , “i”, . . . , “n−1” in an order from asmall threshold voltage. In this case, since a verify read operationsimultaneously verifies whether all data “i” are sufficiently written, areference potential used when a bit line voltage is sensed is set inaccordance with the written data. In addition, as in “0”-data writeoperation, a verify circuit is arranged such that the current of thememory cell is compensated for when it is detected that the data aresufficiently written in the memory cell and the current of the memorycell is not compensated for when it is detected that the data are notsufficiently written in the memory cell. A first data storage unit forstoring data indicating whether data is sufficiently written and asecond data storage unit for storing whether a multivalue level to bewritten is any one of data “1”, . . . , “n−1” are arranged. The firstdata storage unit also serves as a sense amplifier for detecting whetherdata is sufficiently written. In addition, a multivalue (n-value)storage type NAND-cell EEPROm according to a nonvolatile semiconductormemory device is characterized by comprising a bit line write voltageoutput circuit for outputting a bit line voltage in a write operation inaccordance with a desired written state such that, when there is memorycell which does not reach a predetermined written state, a rewriteoperation is performed to only this memory cell.

More specifically, a nonvolatile semiconductor memory device accordingto the third aspect of the present invention includes, as a basicarrangement, a nonvolatile semiconductor memory device comprising amemory cell array in which the memory cells, each of which isconstituted by stacking a charge accumulation layer and a control gateon a semiconductor layer and can be electrically programmed to store atleast three data as multivalue data of threshold voltages of the memorycell, are arranged in a matrix, threshold voltage detection means forcharging a bit line connected to the memory cells so that charging ismade through the memory cells and outputting the multivalue data of thememory cell as multivalue level potentials to the bit line, and a senseamplifier for sensing potentials of the bit line charged by thethreshold voltage detection means, and the nonvolatile semiconductormemory device is characterized by the following embodiments.

-   (1) The nonvolatile semiconductor memory device is characterized in    that the memory cells are connected in series with each other as    units each constituted by memory cells to form a plurality of    NAND-cell structures each having one terminal connected to the bit    line through a first selection gate and the other terminal connected    to a source line through a second selection gate, the threshold    voltage detection means transfers a source line voltage to the bit    line through a corresponding NAND cell to charge the bit line, and    non-selected control gate voltages and first and second selection    gate voltages are controlled such that voltage transfer capabilities    of non-selected memory cells and first and second selection    transistors are sufficiently increased to determine a bit line    voltage at a threshold voltage of a selected memory cell.-   (2) The nonvolatile semiconductor memory device comprises the    plurality of data circuits each functioning as the sense amplifier    and having a function of storing sensed information as data for    controlling write operation states of the memory cells, the write    means for performing a write operation in accordance with contents    of the data circuits respectively corresponding to the plurality of    memory cells in the memory cell array, the write verify means which    uses the threshold voltage detection means to check whether states    of the plurality of memory cells set upon the write operation are    storage states of desired data, and the data circuit content    simultaneous updating means for simultaneously updating the contents    of the data circuits such that a rewrite operation is performed to    only a memory cell, in which data is not sufficiently written, on    the basis of the contents of the data circuits and the states of the    memory cells after a write operation, wherein the data circuit    content simultaneous updating means corrects a bit line potential at    which the storage states of the memory cells set upon the write    operation are output in accordance with the contents of the data    circuits to sense/store the bit line potential as rewrite data,    holds the data storage states of the data circuits until the bit    line potential is corrected, operates the data circuits as sense    amplifiers while the corrected bit line potential is held, and    simultaneously updates the contents of the data circuits, and a    write operation and a data circuit content simultaneous updating    operation based on the contents of the data circuits are repeatedly    performed until the memory cells are set in predetermined written    states, thereby electrically performing a write operation.-   (3) The data circuits control write operation states of the memory    cells in accordance with data stored in the data circuits in a write    operation to perform control such that the states of the memory    cells are changed into predetermined written states or the states of    the memory cells are held in states set prior to the write    operation, and the data circuit content simultaneous updating means    changes data of the data circuits into data for holding the states    of the memory cells in states set prior to the write operation when    a memory cell corresponding to a data circuit in which data for    controlling the memory cells to change the memory cells to have    predetermined written states is stored reaches a predetermined    written state, sets data for controlling the memory cells to change    the memory cells to have predetermined written states in the data    circuits when the memory cell corresponding to the data circuit in    which data for controlling the memory cells to change the memory    cells to have predetermined written states is stored does not reach    the predetermined written state, and sets data for controlling the    states of the memory cells to hold the states of the memory cells in    the states set prior to the write operation in the data circuits,    when data for controlling the states of the memory cells to hold the    states of the memory cells in the states set prior to the write    operation is stored in the data circuits.-   (4) The nonvolatile semiconductor memory device comprises a bit line    potential setting circuit for, of bit line potentials at which    states of the memory cells set upon the write operation are output    by the threshold voltage detection means, when only a bit line    potential corresponding to the data circuits whose contents are data    for controlling the states of the memory cells to hold the states of    the memory cells in the states set prior to the write operation is    sensed by the data circuits, setting a correction bit line potential    at which data for controlling the states of the memory cells to hold    the states of the memory cells in the states set prior to the write    operation is obtained, and wherein, to perform the data circuit    content simultaneous updating operation, a bit line potential at    which the states of the memory cells set upon the write operation    are output with the threshold voltage detection means is corrected    by the bit line potential setting circuit in accordance with the    contents of the data circuits.-   (5) For the nonvolatile semiconductor memory device in which one of    the memory cells has at least three storage data “i” (i=0, 1, . . .    , n−1) to perform a multivalue storing operation, a storage state    corresponding to data “0” being an erased state, each of the data    circuits is constituted by a first data storage unit for storing    information indicating whether a state of a memory cell is held in a    state set prior to a write operation and a second data storage unit    for, when the information of the first data storage unit is not    information for controlling the state of the memory cell such that    the state of the memory cell is held in a state set prior to the    write operation, storing information indicating a written state “i”    (i=1, 2, . . . , n−1) to be stored in the memory cell, and the first    data storage unit having a function of sensing/storing bit line    potentials which are corrected by the bit line potential setting    circuits in accordance with the contents of the data circuits to    perform the data circuit content updating operation and at which the    storage states of the memory cells set upon the write operation are    output with the threshold voltage detection means.-   (6) The first data storage unit has a function of comparing a    reference voltage with a bit line voltage to sense a bit line    potential and a function of sensing/storing a bit line potential    which is corrected by the bit line potential setting circuit in    accordance with the contents of the data circuits using a reference    voltage corresponding to the contents of the data circuits and at    which states of the memory cells set upon the write operation are    output by the threshold voltage detection means.-   (7) The nonvolatile semiconductor memory device comprises a write    prevention bit line voltage output circuit for outputting a write    prevention bit line voltage to a bit line in a write operation when    the information of the first data storage unit is information for    controlling the states of the memory cells to hold the states of the    memory cells in states before the write operation, and an ith write    bit line voltage output circuit for outputting a bit line voltage in    an ith write operation in accordance with information of the second    data storage unit indicating data “i” (i=1, 2, . . . , n−1) to be    stored in the memory cell when the information of the first data    storage unit is not information for controlling the states of the    memory cells to hold the states of the memory cells in states set    prior to the write operation.-   (8) The nonvolatile semiconductor memory device comprises data    inverting means for inverting data of the first data storage unit    for activating the bit line potential setting circuit before the    activation of bit line potential setting circuit, when the data of    the first data storage unit for activating the bit line potential    setting circuit has been inverted to the data of the first data    storage unit for activating the write prevention bit line voltage    output circuit.

In the third aspect of the present invention, after a multivalue datawrite operation is performed, it is simultaneously detected whether thewritten states of the memory cells reach their multivalue level states,respectively. When there is a memory cell which does not reach itsdesired multivalue level, a bit line voltage in a write operation isoutput in accordance with a desired written state such that a rewriteoperation is performed only to this memory cell. The write operation anda verify read operation are repeated, and a data write operation isended when it is confirmed that all the memory cells reach their desiredwritten states, respectively.

As described above, according to the present invention, a time forperforming one write cycle is shortened, and a write operation isrepeated many times within a short time while the degree of progress ofa written state is checked, so that the range of the threshold voltagedistribution of a memory cell in which a data write operation is finallyended can be narrowed at a high speed.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed out in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 is a block diagram showing the schematic arrangement of an EEPROMaccording to the first and second embodiments of the present invention;

FIG. 2 is a circuit diagram showing the detailed arrangement of a memorycell array in the first embodiment;

FIG. 3 is a circuit diagram showing the detailed arrangement of a bitline control circuit in the first embodiment;

FIG. 4 is a timing chart showing a read operation in the firstembodiment;

FIG. 5 is a timing chart showing a write operation in the firstembodiment;

FIG. 6 is a timing chart showing a verify read operation in the firstembodiment;

FIGS. 7A and 7B are timing charts showing data input/output operationsin the first and second embodiments;

FIG. 8 is a view showing the concept of a page serving as a write/readunit in the first and second embodiments;

FIGS. 9A and 9B are flow charts showing a data write algorithm and anadditional data write algorithm in the first and second embodiments,respectively;

FIG. 10 is a graph showing the write characteristics of the memory cellin the first embodiment;

FIG. 11 is a circuit diagram showing the arrangements of a memory cellarray and a bit line control circuit in the second embodiment;

FIG. 12 is a timing chart showing a read operation in the secondembodiment;

FIG. 13 is a timing chart showing a write operation in the secondembodiment;

FIG. 14 is a timing chart showing a verify read operation in the secondembodiment;

FIG. 15 is a graph showing the write characteristics of the memory cellin the second embodiment;

FIG. 16 is a circuit diagram showing the modification of the bit linecontrol circuit in the first embodiment;

FIG. 17 is a circuit diagram showing a modification of the bit linecontrol circuit in the second embodiment;

FIG. 18 is a view showing a unit for an additional data write operationin the first and second embodiments;

FIGS. 19A and 19B are circuit diagrams showing the detailed arrangementof an inverter portion shown in FIG. 3;

FIG. 20 is a circuit diagram showing the arrangement of a NAND cellarray according to the third embodiment of the present invention;

FIGS. 21A and 21B are a circuit diagram and a chart, respectively,showing the read operation of the NAND cell in the third embodiment;

FIG. 22 is a graph showing the relationship between a bit line outputvoltage in a read operation and the threshold voltage of a memory cellin the third embodiment;

FIG. 23 is a graph showing the relationship between a bit line outputvoltage in a read operation and a write time in the third embodiment;

FIG. 24 is a graph showing the relationship between data and a bit lineoutput voltage in a read operation when a binary storing operation isperformed to one memory cell in the third embodiment;

FIG. 25 is a graph showing the relationship between data and a bit lineoutput voltage in a read operation when a ternary storing operation isperformed in one memory cell in the third embodiment;

FIG. 26 is a circuit diagram showing the arrangement of a NOR cell arrayaccording to the fourth embodiment of the present invention;

FIGS. 27A and 27B are a circuit diagram and a chart, respectively,showing the read operation of a NOR cell in the fourth embodiment;

FIG. 28 is a graph showing the relationship between a bit line outputvoltage in a read operation and the threshold voltage of a memory cellin the fourth embodiment;

FIG. 29 is a graph showing the relationship between the bit line outputvoltage in a read operation and a write time in the fourth embodiment;

FIG. 30 is a graph showing the relationship between data and a bit lineoutput voltage in a read operation when a binary storing operation isperformed to one memory cell in the fourth embodiment;

FIG. 31 is a graph showing the relationship between data and a bit lineoutput voltage in a read operation when a ternary storing operation isperformed to one memory cell in the fourth embodiment;

FIG. 32 is a block diagram showing the arrangement of an EEPROMaccording to the third and fourth embodiments;

FIG. 33 is a circuit diagram showing the arrangements of a memory cellarray and a bit line control circuit in the third embodiment;

FIG. 34 is a timing chart showing a read operation in the thirdembodiment;

FIG. 35 is a timing chart showing a write operation in the thirdembodiment;

FIG. 36 is a timing chart showing a verify read operation in the thirdembodiment;

FIG. 37 is a circuit diagram showing the arrangements of a memory cellarray and a bit line control circuit in the fourth embodiment;

FIG. 38 is a timing chart showing a read operation in the fourthembodiment;

FIG. 39 is a timing chart showing a write operation in the fourthembodiment;

FIG. 40 is a timing chart showing a verify read operation in the fourthembodiment; and

FIG. 41 is a circuit diagram showing the arrangement of a column decoderin the third and fourth embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below withreference to the accompanying drawings.

FIG. 1 is a block diagram showing the schematic arrangement of aNAND-cell EEPROM according to the first embodiment of the presentinvention.

A bit line control circuit 2 for controlling a bit line in a read/writeoperation and a word line drive circuit 7 for controlling a word linepotential are arranged for a memory cell array 1. The bit line controlcircuit 2 and the word line drive circuit 7 are selected by a columndecoder 3 and a row decoder 8, respectively. The bit line controlcircuit 2 receives and outputs read/write data from/to an input/outputdata conversion circuit 5 through a data input/output line (IO line).The input/output data conversion circuit 5 converts readout multivalueinformation of a memory cell into binary information to externallyoutput the multivalue information, and converts the binary informationof externally input write data into the multivalue information of amemory cell. The input/output data conversion circuit 5 is connected toa data input/output buffer 6 for controlling a data input/outputoperation with an external circuit. A data write end detection circuit 4detects whether a data write operation is ended. A write control signalgeneration circuit 9 supplies a write control signal to the bit linecontrol circuit 2 and the word line drive circuit 7. A write verifycontrol signal generation circuit 10 supplies a write verify controlsignal to the bit line control circuit 2 and the word line drive circuit7. A data update control signal generation circuit 11 supplies a dataupdate control signal to the bit line control circuit 2.

FIGS. 2 and 3 show the detailed arrangements of the memory cell array 1and the bit line control circuit 2. Memory cells M1 to M8 and selectiontransistors S1 and S2 constitute a NAND cell. One terminal of the NANDcell is connected to a bit line BL, and the other terminal is connectedto a common source line Vs. Selection gates SG1 and SG2 and controlgates CG1 to CG8 are shared by a plurality of NAND cells, and memorycells which share one control gate constitute a page. Each memory cellstores data at a threshold voltage Vt thereof. The memory cell storesdata “0” indicating that the threshold voltage Vt is lower than 0 V,stores “1” indicating that the threshold voltage Vt is greater than 0 Vand lower than 1.5 V, and stores data “2” indicating that the thresholdvoltage Vt is greater than 1.5 V and lower than a power supply voltage.One memory cell can have three states, and nine combinations can beobtained by two memory cells. Of these nine combinations, eightcombinations are used, and data of three bits are stored in the twomemory cells. In this embodiment, data of three bits are stored in apair of adjacent memory cells which share a control gate. In addition,the memory cell array 1 is formed on a dedicated p-type well.

In the bit line control circuit in FIG. 3, clocked synchronous invertersCl1 and Cl2 and clocked synchronous inverters Cl3 and Cl4 constituteflip-flops, respectively, and these flip-flops latch write/read data.The flip-flops are also operated as sense amplifiers. The flip-flopconstituted by the clocked synchronous inverters Cl1 and Cl2 latcheswrite data information indicating whether data “0” or data “1” or “2” isto be written, and latches read data information indicating whether amemory cell stores the information of data “0” or the information ofdata “1” or “2”. The flip-flop constituted by the clocked synchronousinverters Cl3 and Cl4 latches write data information indicating whetherdata “1” or “2” is to be written, and latches read data informationindicating whether a memory cell stores the information of data “2” orthe information of data “0” or “1”.

Of n-channel MOS transistors, an n-channel MOS transistor Qn1 transfersa voltage VPR to a bit line when a precharge signal PRE goes to “H”level. When a bit line connection signal BLC goes to “H” level, ann-channel MOS transistor Qn2 connects the bit line to a main bit linecontrol circuit. N-channel MOS transistors Qn3 to Qn6 and Qn9 to Qn12selectively transfer voltages VBLH, VBLM, and VBLL to the bit line inaccordance with the data latched in the above flip-flops. When signalsSAC2 and SAC1 go to “H” level, n-channel MOS transistors Qn7 and Qn8respectively connect the flip-flops to the bit line. An n-channel MOStransistor Qn13 is arranged to detect whether all the data of one pagelatched in the flip-flops are identical to each other. When columnselection signals CSL1 and CSL2 go to “H” level, n-channel MOStransistors Qn14 and Qn15 selectively connect a corresponding one of theflip-flops to data input/output line IOA or IOB, and n-channel MOStransistors Qn16 and Qn17 selectively connect a corresponding one of theflip-flops to the data input/output line IOA or

Although an inverter portion is roughly shown in FIG. 3 as shown in FIG.19(a), the inverter portion has the circuit arrangement shown in FIG.19(b).

The operation of the EEPROM arranged as described above will bedescribed below with reference to FIGS. 4 to 6. FIG. 4 shows readoperation timings, FIG. 5 shows write operation timings, and FIG. 6shows verify read operation timings. Each of FIGS. 4, 5, and 6 shows acase wherein the control gate CG4 is selected.

A read operation is executed by two basic cycles. In the first readcycle, the voltage VPR becomes a power supply voltage Vcc to prechargethe bit line, and the precharge signal PRE goes to “L” level to causethe bit line to float. Subsequently, the selection gates SG1 and SG2 andthe control gates CG1 to CG3 and CG5 to CG8 are set to be the powersupply voltage Vcc. At the same time, the control gate CG4 is set to be1.5 V. Only when the threshold voltage of a selected memory cell is setto be 1.5 V or more, i.e., data “2” is written in this memory cell, thebit line is kept at “H” level.

Thereafter, sense activation signals SEN2 and SEN2B go to “L” level and“H” level, respectively, and latch activation signals LAT2 and LAT2B goto “L” level and “H” level, respectively, thereby resetting theflip-flop constituted by the clocked synchronous inverters Cl3 and Cl4.The signal SAC2 goes to “H” level to connect the flip-flop constitutedby the clocked synchronous inverters Cl3 and Cl4 to the bit line. Afterthe sense activation signals SEN2 and SEN2B go to “H” level and “L”level, respectively, to sense a bit line potential, the latch activationsignals LAT2 and LAT2B go to “H” level and “L” level, respectively, andthe information of data “2” or data “1” or “0” is latched in theflip-flop constituted by the clocked synchronous inverters Cl3 and Cl4.

In the second read cycle, unlike the first read cycle, the voltage ofthe selection control gate CG4 is not set to be 1.5 V but is set to be 0V, and signals SEN1, SEN1B, LAT1, LAT1B, and SAC1 are output in place ofthe signals SEN2, SEN2B, LAT2, LAT2B, and SAC2. Therefore, in the secondread cycle, the information of data “0” or data “1” or “2” is latched inthe flip-flop constituted by the clocked synchronous inverters Cl1 andCl2.

Data written in the memory cells are read out by the two read cyclesdescribed above.

The data of the memory cells are erased prior to a data write operation,and the threshold voltage Vt of each of the memory cells is set to beless than 0 V. The p-type well, the common source line Vs and, theselection gates SG1 and SG2 are set to be 20 V, and the control gatesCG1 to CG8 are set to be 0 V, thereby performing an erase operation.

In the write operation, the precharge signal PRE goes to “L” level tocause the bit line to float. The selection gate SG1 and the controlgates CG1 to CG8 are set to be Vcc. The selection gate SG2 is set to be0 V during the write operation. At the same time, signals VRFY1, VRFY2,FIM, and FIH are set to be Vcc. In a “0”-data write operation, since theflip-flop constituted by the clocked synchronous inverters Cl1 and Cl2latches data such that an output from the clocked synchronous inverterCl1 is set at “H” level, the bit line is charged by the voltage Vcc. Inthe “1”- or “2”-data write operation, the bit line is set to be 0 V.

Subsequently, the selection gate SG1, the control gates CG1 to CGS, thesignals BLC and VRFY1, and a voltage VSA are set to be 10 V, the voltageVBLH is set to be 8 V, and the voltage VBLM is set to be 1 V. In the“1”-data write operation, since the flip-flop constituted by the clockedsynchronous inverters Cl3 and Cl4 latches data such that an output fromthe clocked synchronous inverter Cl3 goes to “H” level, a voltage of 1 Vis applied to the bit line BL. In a “2”-data write operation, the bitline is set to be 0 V. In a “0”-data write operation, the bit line isset to be 8 V. Thereafter, the selected control gate CG4 is set to be 20V.

In a “1”- or “2”-data write operation, electrons are injected into thecharge accumulation layers of the memory cells by the potentialdifference between the bit line BL and the control gate CG4. In the“1”-data write operation, amounts of charges to be injected into thecharge accumulation layers of the memory cells must be smaller thanthose in the “2”-data write operation. For this reason, the bit line BLis set to be 1 V to relax the potential difference between the bit lineBL and the control gate CG4 to 19 V. However, even when the potentialdifference is not relaxed, the same effect as described above can beobtained by adjusting a write time. In a “0”-data write operation, thethreshold voltages of the memory cells are not effectively changed by abit line voltage of 8 V.

Upon completion of the write operation, the selection gate SG1 and thecontrol gates CG1 to CG8 are set to be 0 V, and then the voltage of thebit line BL set to be 8 V in the “0”-data write operation is reset to 0V with a time lag. This is because, when the order of the settingoperations is reversed, a “2”- or “1”-data-written state is temporarilyset, and erroneous data is written in the “0”-data write operation.

After the write operation, a verify read operation is performed to checkthe written state of the memory cell and perform an additional writeoperation to only a memory cell in which data is not sufficientlywritten. During the verify read operation, the voltages VBLH, VBLL, andFIM are set to be Vcc, 0 V, and 0 V, respectively.

The verify read operation is executed by two basic cycles. Each of thebasic cycles is almost identical to the second read cycle except thatthe voltage of the selected control gate CG4 and signals VRFY1, VRFY2,and FIH are output (only the signal VRFY1 is output in the first verifyread cycle). The signals VRFY1, VRFY2, and FIH are output before thesignals SEN1, SEN1B, LAT1, and LAT1B go to “L” level, “H” level, “L”level and “H” level, respectively, after the selection gates SG1 and SG2and the control gates CG1 to CG8 are reset to 0 V. In other words, thesignals VRFY1, VRFY2, and FIH are output before the flip-flopconstituted by the clocked synchronous inverters Cl1 and Cl2 is resetafter the potential of the bit line is determined by the thresholdvoltages of the memory cells. The potential of the selected control gateCG4 is set to be 2 V (first cycle) and 0.5 V (second cycle) in theverify read operation which are higher than 1.5 V (first cycle) and 0 V(second cycle) in the read operation to assure a threshold voltagemargin of 0.5 V.

In this case, data (data 1) latched in the flip-flop constituted by theclocked synchronous inverters Cl1 and Cl2, data (data 2) latched in theflip-flop constituted by the clocked synchronous inverters Cl3 and Cl4,and the voltage of the bit line BL determined by the threshold voltageof a selected memory cell will be described below. The data 1 controls a“0”-data write operation or a “1”- or “2”-data write operation. Then-channel MOS transistor Qn3 is set in an “ON” state when the “0”-datawrite operation is performed, and the n-channel MOS transistor Qn6 isset in an “ON” state when “1”- or “2”-data write operation is performed.The data 2 controls a “1”-data write operation or a “2”-data writeoperation. The n-channel MOS transistor Qn10 is set in an “ON” statewhen the “1”-data write operation is performed, and the n-channel MOStransistor Qn11 is set in an “ON” state when the “2”-data writeoperation is performed.

In the first verify read cycle in the “0”-data write operation (initialwrite data is data “0”), the data of the memory cell is data “0”. Forthis reason, when the control gate CG4 is set to be 2 V, the memory cellcauses a bit line potential to go to “L” level. Thereafter, when signalVRFY1 goes to “H” level, the potential of the bit line BL goes to “H”level.

In the first verify read cycle in the “1”-data write operation (initialwrite data is data “1”), since the data of the memory cell is to be “1”,the threshold voltage of the memory cell is less than 1.5 V. When thecontrol gate CG4 is set to be 2 V, the memory cell causes the bit linepotential to go to “L” level. In this case, even when the initial writedata is data “1”, when data “1” is sufficiently written in the selectedmemory cell by the previously performed verify read cycles, the data 1is set to be data “0”. In this case, when the signal VRFY1 goes to “H”level later, the potential of the bit line BL goes to “H” level ((1) inFIG. 6). In cases except for the above case, the potential of the bitline BL goes to “L” level ((2) in FIG. 6).

In the first verify read cycle in the “2”-data write operation (initialwrite data is data “2”), when the data of the selected memory cell isnot data (data “2” is not sufficiently written), and the control gateCG4 is set to be 2 V, the memory cell causes the bit line potential togo to “L” level ((5) in FIG. 6). When data “2” is sufficiently writtenin the selected memory cell, even when the control gate CG4 is set to be2 V, the bit line potential is kept at “H” level ((3) and (4) in FIG.6). (3) in FIG. 6 indicates a case wherein data “2” is sufficientlywritten in the memory cell in advance, and the data 1 is converted intodata for controlling the “0”-data write operation by the previouslyperformed verify read cycles. In this case, when the signal VRFY1 goesto “H” level, the bit line BL is charged by and voltage VBLH again.

In the second verify read cycle in the “0”-data write operation (initialwrite data is data “0”), the data of the memory cell is data “0”. Forthis reason, when the control gate CG4 is set to be 0.5 V, the memorycell causes the bit line potential to go to “L”. Thereafter, when thesignal VRFY1 goes to “H” level, the potential of the bit line BL goes to“H” level.

In the second verify read cycle in the “1”-data write operation (initialwrite data is data “1”), the data of the selected memory cell is notdata “1” (data “1” is not sufficiently written), and the control gateCG4 is set to be 0.5 V, the memory cell causes the bit line potential togo to “L” level ((8) in FIG. 6). When data “1” is sufficiently writtenin the selected memory cell, even when the control gate CG4 is set to be0.5 V, the bit line potential is kept at “H” level ((6) and (7) in FIG.6). (6) in FIG. 6 indicates a case wherein data “1” is sufficientlywritten in the memory cell in advance by previous verify read cycles,and the data 1 is converted into data for controlling the “0”-data writeoperation. In this case, when the signal VRFY1 goes to “H” level, thebit line BL is charged b the voltage VBLH again.

In the second verify read cycle in the data “2” read operation (initialwrite data is data “2”), the data of the memory cell is to be data “2”.For this reason, assuming that the threshold voltage of the memory cellis 0.5 V or more, even when data “2” is sufficiently written or is notsufficiently written in the memory cell, and the control gate CG4 is setto be 0.5 V, the bit line potential is kept at “H” level ((9) and (10)in FIG. 6). When data “2” is not sufficiently written in the memorycell, and the threshold voltage of the memory cell is 0.5 V or less, thebit line potential goes to “L” level ((11) in FIG. 6).

Thereafter, when the signals VRFY1, VRFY2, and FIH go to “H” level, data“2” is sufficiently written, and the data 1 is converted into data forcontrolling a “0”-data write operation, the potential of the bit line BLgoes to “H” level ((9) in FIG. 6). In other cases except for the abovecase, the potential of the bit line BL goes to “L” level ((10) and (11)in FIG. 6).

With the above verify read operation, rewrite data are set as shown inthe following table (Table 1) on the basis of the write data and thewritten states of the memory cells.

TABLE 1 Write Data 0 0 0 1 1 2 2 2 Cell Data 0 1 2 0 1 0 1 2 RewriteData 0 0 0 1 0 2 2 0

As is apparent from Table 1, data “1” is rewritten in only a memory cellin which data “1” is not sufficiently written, and data “2” is rewrittenin only a memory cell in which “2” is not sufficiently written. Inaddition, when data are sufficiently written in all the memory cells,the n-channel MOS transistors Qn13 of all the columns are set in an“OFF” state, and data write operation end information is output by asignal PENDB.

FIGS. 7A and 7B show data input/output operation timings. FIG. 7A showsa data input timing, and FIG. 7B shows a data output timing. After threeexternal data input cycles are performed, data to be input to the bitline control circuit 2 is generated and output from the input/outputdata conversion circuit 5. External data (X₁,X₂,X₃) of three bits areconverted into data (Y₁, Y₂) for two memory cells. In the bit linecontrol circuit 2, the converted data are set in a register R1constituted by the clocked synchronous inverters Cl1 and Cl2 and aregister R2 constituted by the clocked synchronous inverters Cl3 andCl4. This setting is performed through the data input/output lines IOAand IOB. Readout data latched in the registers R1 and R2 are transferredto the input/output data conversion circuit 5 through the datainput/output lines IOA and IOB, converted, and then output. Columnselection signals CSL1i and CSL2i are set to be the same signal, and thedata input/output lines IOA and IOB are divided into two systems suchthat two registers of the same column can be easily accessed at once.Therefore, an access time can be effectively shortened.

The following table (Table 2) shows the relationships between externaldata (X₁,X₂,X₃) of three bits, two data (Y₁, Y₂) of the memory cells,and the data of the registers R1 and R2 respectively corresponding tothe data Y₁ and Y₂ in a data input operation.

TABLE 2 IOA Line Data Input Cell Cell Y₁ Cell Y2 Data Data Regis- Regis-Regis- Regis- X₁ X₂ X₃ Y₁ Y₂ ter R1 ter R2 ter R1 ter R2 0 0 0 0 0 H — H— 0 0 1 0 2 H — L L 0 1 0 0 1 H — L H 0 1 1 1 2 L H L L 1 0 0 1 0 L H H— 1 0 1 1 1 L H L H 1 1 0 2 0 L L H — 1 1 1 2 1 L L L H Pointer 2 2 L LL L write instruction

Each register data is expressed by the voltage level of the input/outputline IOA in a data transfer operation. Since the data input/output lineIOB is obtained by inverting the data input/output line IOA, the datainput/output line IOB is not illustrated. The following table (Table 3)shows the relationships of Table 2 in a data output operation.

TABLE 3 IOA Line Data Cell Y₁ Cell Y2 Cell Output Regis- Regis- Regis-Regis- Data Data ter R1 ter R2 ter R1 ter R2 Y₁ Y₂ X₁ X₂ X₃ L L L L 0 00 0 0 L L H H 0 2 0 0 1 L L H L 0 1 0 1 0 H L H H 1 2 0 1 1 H L L L 1 01 0 0 H L H L 1 1 1 0 1 H H L L 2 0 1 1 0 H H H L 2 1 1 1 1 H H H H 2 2Pointer flag output

In this embodiment, the level of the data input/output line IOA in aninput operation and the level of the data input/output line IOA in anoutput operation are inverted with respect to the same data.

Of nine combinations of the two data (Y₁, Y₂) of the memory cells, onecombination is an extra combination. For this reason, this extracombination can be used as file management information such as pointerinformation. In this case, the pointer information corresponds to celldata (Y₁, Y₂)=(2,2).

FIG. 8 shows the concept of a page serving as a data write unit whenviewed from a microprocessor or the like for controlling an EEPROM. Inthis case, one page is defined by N bytes, and addresses (logicaladdresses) when viewed from a microprocessor or the like arerepresented. For example, when write data is input into only an area 1(logical addresses 0 to n), and n=3m+2 (m=0, 1, 2, . . . ) is satisfied,data (X₁,X₂,X₃) are always completed. For this reason, no problem isposed. Since only data X₁ is input when n=3m, data X₂=0 and X₃=0 aregenerated inside the EEPROM, so that data (X₁,X₂,X₃) are input to theinput/output data conversion circuit 5. When n=3m+1, data X₃=0 isgenerated inside the EEPROM. When the address n is equal to the addressN, the same effect as described above can be obtained.

After a data write operation is performed in the area 1 (all write datain an area 2 are “0”), when a data write operation is additionallyperformed in an area 2, the data in the area 1 are read out, and thewrite data in the area 2 is added to the readout data and input them.Alternatively, the data in the area 1 are read out. When the startaddress of the area 2 is n+1=3m, all the data in the area 1 may be setto be data “0”; when the start address is n+1=3m+2, data at addressesn−1 and n may be added as data X₁ and X₂ to data X₃ at address n+1, andall data at addresses up to address n−2 in the area 1 may be set to bedata “0”; and when the start address is n+1=3m+1, data at address n maybe added as data X₁ to data X₂ and X₃ at addresses n+1 and n+2, and alldata at addresses up to address n−1 may be set to be data “0”. Theseoperations can be easily, automatically performed inside the EEPROM. Thecombinations between the data (X₁,X₂,X₃) and data (Y₁, Y₂) are formed asshown in Tables 2 and 3 such that the additional data write operationcan be performed. The relationships between the data (X₁,X₂,X₃) and thedata (Y₁, Y₂) shown in Tables 2 and 3 are only examples, and therelationships between the data (X₁,X₂,X₃) and the data (Y₁, Y₂) are notlimited to the relationships shown in Tables 2 and 3. In addition, evenwhen the number of areas is three or more, additional data can bewritten in the same manner as described above.

FIG. 9A shows a data write algorithm. After a data loading operation isperformed, a write operation, a verify read operation, and a write enddetecting operation are repeatedly performed. The operations enclosed bya dotted line are automatically performed in the EEPROM.

FIG. 9B shows an additional data write algorithm. After a read operationand a data loading operation are performed, a verify read operation, awrite end detecting operation, and a write operation are repeatedlyperformed. The operations enclosed by a dotted line are automaticallyperformed in the EEPROM. The verify read operation is performed afterthe data loading operation is performed because data is prevented frombeing written in a memory cell in which data “1” or “2” is written inadvance. If the verify read operation is not performed after the dataloading operation is performed, an excessive write operation may beperformed.

FIG. 10 shows write characteristics with respect to the thresholdvoltage of a memory cell in the EEPROM described above. A writeoperation in a memory cell in which data “1” is to be written and awrite operation in a memory cell in which data “2” is to be written areperformed at once, and write periods of time are independently set forthese memory cells.

The following table (Table 4) shows the potentials at several positionsof the memory cell array in an erase operation, a write operation, and averify read operation.

TABLE 4 Verify Write Read Operation Erase Operation Read Operation FirstSecond Operation “0” “1” “2” First Cycle Second Cycle Cycle Cycle BL 20V  8 V  1 V 0 V “H” only when “L” only when See FIG. 6 data “2” is readdata “0” is read SG1 20 V  10 V 5 V 5 V CG1 0 V 10 V 5 V 5 V CG2 0 V 10V 5 V 5 V CG3 0 V 10 V 5 V 5 V CG4 0 V 20 V 1.5 V 0 V 2 V 0.5 V CG5 0 V10 V 5 V 5 V CG6 0 V 10 V 5 V 5 V CG7 0 V 10 V 5 V 5 V CG8 0 V 10 V 5 V5 V SG2 20 V   0 V 5 V 5 V Vs 20 V   0 V 0 V 0 V P well 20 V   0 V 0 V 0V

FIG. 11 shows the detailed arrangements of a memory cell array 1 and abit line control circuit 2 in a NOR-cell EEPROM according to the secondembodiment of the present invention. A NOR cell is constituted by only amemory cell M10. One terminal of the NOR cell is connected to a bit lineBL, and the other terminal is connected to a common ground line. Memorycells M which share one control gate WL constitute a page. Each of thememory cells M stores data at a threshold voltage Vt thereof. The memorycell stores data “0” indicating that the threshold voltage Vt is notless than Vcc, stores data “1” indicating that the threshold voltage Vtis lower than Vcc and not less than 2.5 V, and stores data “2”indicating that the threshold voltage Vt is lower than 2.5 V and notless than 0 V. One memory cell can have three states, and ninecombinations can be obtained by two memory cells. Of these ninecombinations, eight combinations are used, and data of three bits arestored in the two memory cells. In this embodiment, data of three bitsare stored in a pair of adjacent memory cells which share a controlgate.

A flip-flop is constituted by clocked synchronous inverters Cl5 and Cl6,and a flip-flop is constituted by clocked synchronous inverters Cl7 andCl8. These flip-flops latch write/read data. The flip-flops are alsooperated as sense amplifiers. The flip-flop constituted by the clockedsynchronous inverters Cl5 and Cl6 latches write data informationindicating whether data “0” or data “1” or “2” is to be written, andlatches read data information indicating whether a memory cell storesthe information of data “0” or the information of data “1” or “2”. Theflip-flop constituted by the clocked synchronous inverters Cl7 and Cl8latches write data information indicating whether data “1” or “2” is tobe written, and latches read data information indicating whether amemory cell stores the information of data “2” or the information ofdata “0” or “1”.

Of n-channel MOS transistors, an n-channel MOS transistor Qn18 transfersa voltage VPR to a bit line when a precharge signal PRE goes to “H”level. When a bit line connection signal BLC goes to “H” level, ann-channel MOS transistor Qn19 connects the bit line to a main bit linecontrol circuit. N-channel MOS transistors Qn20 to Qn23 and Qn25 to Qn28selectively transfer voltages VBLH, VBLM, and a voltage of 0 V to thebit line in accordance with the data latched in the above flip-flops,when signals SAC2 and SAC1 go to “H” level, n-channel MOS transistorsQn24 and Qn29 respectively connect the flip-flops to the bit line. Ann-channel MOS transistor Qn30 is arranged to detect whether all the dataof one page latched in the flip-flops are identical to each other. Whencolumn selection signals CSL1 and CSL2 go to “H” level, n-channel MOStransistors Qn31 and Qn32 selectively connect a corresponding one of theflip-flops to a data input/output line IOA or IOB, and n-channel MOStransistors Qn33 and Qn34 selectively connect a corresponding one of theflip-flops to the data input/output line IOA or IOB.

The operation of the EEPROM arranged as described above will bedescribed below with reference to FIGS. 12 to 14. FIG. 12 shows readoperation timings, FIG. 13 shows write operation timings, and FIG. 14shows verify read operation timings.

A read operation is executed by two basic cycles. In the first readcycle, the voltage VPR becomes a power supply voltage Vcc to precharge abit line, and the precharge signal PRE goes to “L” level to cause thebit line to float. Subsequently, the control gate WL is set to be 2.5 V.Only when the threshold voltage Vt of a selected memory cell is set tobe 2.5 V or less, i.e., data “2” is written in this memory cell, the bitline goes to “L” level.

Thereafter, sense activation signals SEN2 and SEN2B go to “L” level and“H” level, respectively, and latch activation signals LAT2 and LAT2B goto “L” level and “H” level, respectively, thereby resetting theflip-flop constituted by the clocked synchronous inverters Cl7 and Cl8.The signal SAC2 goes to “H” level to connect the flip-flop constitutedby the clocked synchronous inverters Cl7 and Cl8 to the bit line. Afterthe sense activation signals SEN2 and SEN2B go to “H” level and “L”level, respectively, to sense a bit line potential, the latch activationsignals LAT2 and LAT2B go to “H” level and “L” level, respectively, andthe information of data “2” or “1” or data “0” is latched in theflip-flop constituted by the clocked synchronous inverters Cl7 and Cl8.

In the second read cycle, unlike the first read cycle, the voltage ofthe selection control gate WL is not set to be 2.5 V but is set to beVcc, and signals SEN1, SEN1B, LAT1, LAT1B, and SAC1 are output in placeof the signals SEN2, SEN2B, LAT2, LAT2B, and SAC2. Therefore, in thesecond read cycle, the information of data “0” or data “1” or “2” islatched in the flip-flop constituted by the clocked synchronousinverters Cl5 and Cl6.

Data written in the memory cells are read out by the two read cyclesdescribed above.

The data of the memory cells are erased prior to a data write operation,and the threshold voltage Vt of each of the memory cells is set to beVcc or more. The control gate WL is set to be 20 V, and the bit line isset to be 0 V, thereby performing an erase operation.

In the write operation, the precharge signal PRE goes to “L” level tocause the bit line to float. Signals VRFY1, VRFY2, FIM, and FIL are setto be Vcc. In a “0”-data write operation, since the flip-flopconstituted by the clocked synchronous inverters Cl5 and Cl6 latchesdata such that an output from the clocked synchronous inverter Cl5 goesto “H” level, the bit line is set to be 0 V. In the “1”- or “2”-datawrite operation, the bit line is set to be Vcc.

Subsequently, the signals BLC, VRFY2, FIM, and FIL and a voltage VSA areset to be 10 V, the voltage VBLH is set to be 8 V, and the voltage VBLMis set to be 7 V. In the “1”-data write operation, since the flip-flopconstituted by the clocked synchronous inverters Cl7 and Cl8 latchesdata such that an output from the clocked synchronous inverter Cl7 goesto “H” level, a voltage of 7 V is applied to the bit line BL. In a“2”-data write operation, the bit line is set to be 8 V. In a “0”-datawrite operation, the bit line is set to be 0 V. Thereafter, the selectedcontrol gate WL is set to be −12 V.

In a “1”- or “2”-data write operation, electrons are discharged from thecharge accumulation layers of the memory cells by the potentialdifference between the bit line BL and the control gate WL, and thethreshold voltages of the memory cells decrease. In the “1”-data writeoperation, a total amount of charge to be removed from the chargeaccumulation layers of the memory cells must be smaller than that in the“2”-data write operation. For this reason, the bit line BL is set to be7 V to relax the potential difference between the bit line BL and thecontrol gate WL to 19 V. In a “0”-data write operation, the thresholdvoltages of the memory cells are not effectively changed by a bit linevoltage of 0 V.

After the write operation, a verify read operation is performed to checkthe written states of the memory cells and perform an additional writeoperation to only a memory cell in which data is not sufficientlywritten. During the verify read operation, the voltages VBLH and FIM areset to be Vcc and 0 V, respectively. The verify read operation isexecuted through two basic cycles. Each of the basic cycles is almostidentical to the second read cycle except that the voltage of theselected control gate WL and signals VRFY1, VRFY2, and FIL are output(only the signal VRFY1 is output in the first verify read cycle). Thesignals VRFY1, VRFY2, and FIL are output before the signals SEN1, SEN1B,LAT1, and LAT1B go to “L” level, “H” level, “L” level and “H” level,respectively, after the control gate WL is reset to 0 V. In other words,the signals VRFY1, VRFY2, and FIL are output before the flip-flopconstituted by the clocked synchronous inverters Cl5 and Cl6 is resetafter the potential of the bit line is determined by the thresholdvoltages of the memory cells. The potential of the selected control gateWL is set to be 2 V (first cycle) and 4 V (second cycle) which arerespectively lower than 2.5 V (first cycle) and Vcc (second cycle) inthe read operation to assure a threshold voltage margin.

In this case, data (data 1) latched in the flip-flop constituted by theclocked synchronous inverters Cl5 and Cl6, data (data 2) latched in theflip-flop constituted by the clocked synchronous inverters Cl7 and Cl8,and the voltage of the bit line BL determined by the threshold voltageof a selected memory cell will be described below. The data 1 controls a“0”-data write operation or a “1”- or “2”-data write operation. Then-channel MOS transistor Qn20 is set in an “ON” state when the “0”-datawrite operation is performed, and the n-channel MOS transistor Qn23 isset in an “ON” state when the “1”-or “2”-data write operation isperformed. The data 2 controls a “1”-data write operation or “2”-datawrite operation. The n-channel MOS transistor Qn26 is set in an “ON”state when the “1”-data write operation is performed, and the n-channelMOS transistor Qn27 is set in an “ON” state when the “2”-data writeoperation is performed.

In the first verify read cycle in the “0”-data write operation (initialwrite data is data “0”), the data of the memory cell is data “0”. Forthis reason, when the control gate WL is set to be 2 V, the bit linepotential is kept at “H” level. Thereafter, when signal VRFY1 goes to“H” level, the potential of the bit line BL goes to “L” level.

In the first verify read cycle in the “1”-data write operation (initialwrite data is data “1”), since the data of the memory cell is to be data“1”, the threshold voltage of the memory cell is 2.5 V or more. When thecontrol gate WL is set to be 2 V, the bit line potential is kept at “H”level. Thereafter, the signal VRFY1 goes to “H” level. In this case,when data “1” is sufficiently written by the previous verify read cyclesin advance, and the data 1 is converted into data for controlling the“0”-data write operation, the potential of the bit line BL goes to “L”level ((2) in FIG. 14); otherwise, “H” level ((1) in FIG. 14).

In the first verify read cycle in the “2”-data write operation (initialwrite data is data “2”), when the data of the selected memory cell isnot data “2” (data “2” is not sufficiently written), even when thecontrol gate WL is set to be 2 V, the bit line potential is kept at “H”level ((3) in FIG. 14). When data “2” is sufficiently written in theselected memory cell, and the control gate WL is set to be 2 V, thememory cell causes the bit line potential to go to “L” level ((4) and(5) in FIG. 14). (5) in FIG. 14 indicates a case wherein data “2” issufficiently written in the memory cell by the previous verify readcycles in advance, and the data 1 is converted into data for controllingthe “0”-data write operation by the previous verify read cycle. In thiscase, when the signal VRFY1 goes to “H” level, the bit line BL isgrounded.

In the second verify read cycle in the “0”-data write operation (initialwrite data is data “0”), assume the data of the memory cell is data “0”.For this reason, even when the control gate WL is set to be 4 V, the bitline potential is kept at “H” level. Thereafter, when the signal VRFY1goes to “H” level, the potential of the bit line BL goes to “L” level.

In the second verify read cycle in the “1”-data write operation (initialwrite data is date “1”), if the data of the selected memory cell is notdata “1” (data “1” is not sufficiently written), even when the controlgate WL is set to be 4 V, the bit line potential “H” is kept at “H”level ((6) in FIG. 14). When data “1” is sufficiently written in theselected memory cell, when the voltage of the control gate WL becomes 4V, the bit line potential goes to “L” level ((7) and (8) in FIG. 14).(8) in FIG. 14 indicates a case wherein data “1” is sufficiently writtenin the memory cell by the previous verify read cycle in advance, and thedata 1 is converted into data for controlling the “0”-data writeoperation. In this case, when the signal VRFY1 goes to “H” level, thebit line BL is grounded.

In the second verify read cycle in the “2”-data write operation (initialwrite data is data “2”), the data of the memory cell is to be data “2”.For this reason, assuming that the threshold voltage of the memory cellis 4 V or less, even when data “2” is sufficiently written or is notsufficiently written in the memory cell, and the control gate WL is setto be 4 V, the bit line potential goes to “L” level ((10) and (11) inFIG. 14). when data “2” is not sufficiently written in the memory cell,and the threshold voltage of the memory cell is 4 V or more, the bitline potential goes to “H” level ((9) in FIG. 14).

Thereafter, when the signals VRFY1, VRFY2, and FIL go to “H” level, data“2” is sufficiently written, and the data 1 is converted into data forcontrolling a “0”-data write operation. In this case, the potential ofthe bit line BL goes to “L” level ((11) in FIG. 14); otherwise, “H”level ((9) and (10) in FIG. 14).

When the above verify read operation, rewrite data are set as shown inthe following Table 1 on the basis of the write data and the writtenstates of the memory cells, as in the first embodiment. In addition,when data are sufficiently written in all the memory cells, then-channel MOS transistors Qn30 of all columns are set in an “OFF” state,and data write operation end information is output by a signal PENDB.

Data input/output operation timings, a data write algorithm, and anadditional data write algorithm in the second embodiment are the same asthose of the first embodiment as shown in FIGS. 7 to 9 and Tables 2 and3.

FIG. 15 shows write characteristics with respect to the thresholdvoltages of memory cells in the EEPROM described above. A writeoperation in a memory cell in which data “1” is to be written and awrite operation in a memory cell in which data “2” is to be written areperformed at once, and write periods of time are independently set forthese memory cells.

The following table (Table 5) shows the potentials at BL and WL of thememory cell array in an erase operation, a write operation, and a verifyread operation.

TABLE 5 Verify Write Read Operation Erase Operation Read Operation FirstSecond Operation “0” “1” “2” First Cycle Second Cycle Cycle Cycle BL  0V 0 V 7 V 8 V “L” only when “H” only when See FIG. 14 data “2” is readdata “0” is read WL 20 V −12 V 2.5 V 5 V 2.0 V 4.0 V

The circuits shown in FIGS. 3 and 11 can be modified into, e.g., thecircuits shown in FIGS. 16 and 17, respectively. Referring to FIG. 16,the n-channel MOS transistors Qn3 and Qn4 are replaced with p-channelMOS transistor Qp1 and Qp2, respectively. Referring to FIG. 17, then-channel MOS transistors Qn22 and Qn23 and the n-channel MOStransistors Qn25 to Qn28 are replaced with p-channel MOS transistors Qp3to Qp8. with the above arrangement, a voltage which can be transferredthrough transistors can be prevented from dropping according to thethreshold voltage of the n-channel MOS transistor. In this embodiment,since it is required only to increase the voltage VSA to 8 V, thebreakdown voltage of the transistors constituting the above circuit canbe decreased. A signal VRFY1B in FIG. 16 is the inverted signal of theVRFY1 in FIGS. 2 and 3. Signals VRFY2B, FILB, and FIMB are invertedsignals of the signals VRFY2, FIL, and FIM in FIG. 11, respectively.

The additional data write operation is described in FIG. 8. For example,as shown in FIG. 18, it is one effective method that one page is dividedinto areas to easily perform an additional data write operation. In thisembodiment, one area is constituted by 22 memory cells set every 32logical addresses. In this manner, an additional data write operation inunits of areas can be easily performed. More specifically, whenadditional data is to be written in the area 2, the write data in allareas except for the area 2 are set to be data “0”, and the additionaldata may be written in the area 2 according to the data write algorithmshown in FIG. 9A. Each area may have a size except for the size of eachof the areas shown in FIG. 18.

FIG. 20 shows a memory cell array 1 of a NAND-cell EEPROM according tothe third embodiment of the present invention. The memory cell array 1is formed on a p-type well or a p-type substrate, and eight memory cellsM1 to M8 are connected in series between a selection transistor S1connected to a bit line BL and a selection transistor S2 connected to acommon source line Vs, thereby constituting one NAND cell. The selectiontransistors S (S1 and S2) have selection gates SG (SG1 and SG2),respectively. The memory cells have floating gates (charge accumulationlayers) and control gates CG (CG1 to CGS) which are stacked and formedon each other. The memory cells store information by using amounts ofcharges accumulated in the floating gates of the memory cells. Theamounts of accumulated charges can be read out as the threshold voltagesof the corresponding memory cells.

In the present invention, such a threshold voltage is read out as shownin FIGS. 21A and 21B. In this case, the memory cell M2 having thecontrol gate CG2 is selected. As shown in FIG. 21A, a voltage is appliedto each portion, and the bit line BL is set in a floating state. Whenthe bit line BL is reset to 0 V in advance, the bit line BL is chargedby the common source line Vs through the NAND cell. The selection gatevoltages and control gate voltages are controlled such that thepotential of the charged bit line BL is determined by the thresholdvoltage of the selected memory cell M2.

In this embodiment, the selection gates SG1 and SG2, the control gatesCG1 and CG3 to CG8 are set to be 6 V, the selected control gate CG2 isset to be 2 V, and the common source line Vs is set to be 6 V. Thevoltage waveforms of these parts are shown in FIG. 21B. In this case, athreshold voltage of 2 V or less can be read out. When the thresholdvoltage of each non-selected memory cell is controlled to be 2.5 V orless, a threshold voltage of −1.5 V or more can be read out. When thepotential of the bit line BL is 0 V, a threshold voltage of 2 V or morecan be read out; when the bit line potential is 3.5 V, a thresholdvoltage of −1.5 V or less can be read out. When the voltages of theselection gates SG1 and SG2 and the non-selected control gates CG1 andCG3 to CG8 are made sufficiently high, a threshold voltage of up to −4 Vcan also be read out.

The relationship between the threshold voltage of the memory cell and abit line output voltage in this case is shown in FIG. 22. Whencalculation is performed on the basis of a threshold voltage obtainedwhen a back bias voltage is 0 V, a solid line in FIG. 22 is obtained.However, the bit line voltage becomes equal to the back bias voltage inpractice, and the bit line output voltage decreases as indicated by achain line in FIG. 22. For the sake of descriptive convenience, athreshold voltage is obtained in consideration of a back bias voltagehereinafter, unless otherwise specified.

After electrons are discharged from the floating gate of the memory cellby an erase operation, electrons are injected into the floating gate bya write operation performed according to write data. FIG. 23 shows therelationship between a write time and a bit line output voltage in aread operation when a bit line output voltage in the read operation isnot limited to the threshold voltage of each non-selected memory cell.For example, when the voltage of the common source line in the readoperation is 3 V, the bit line output voltage does not change unless thethreshold voltage becomes −1 V or more, as a result of electroninjection into the floating gate. Even when the voltage of the commonsource line is 6 V, when the threshold voltage of each non-selectedmemory cell is positive, the bit line output voltage in the readoperation is limited.

When one memory cell has two states (data “0” and data “1”), forexample, as shown in FIG. 24, a state in which the bit line outputvoltage in a read operation becomes 3 to 4 V (threshold voltage of about−2 V to −1 V) may be set as data “0” (erased state), and a state inwhich the bit line output voltage becomes 1 to 2 V (threshold voltage ofabout 0 to 1 V) may be set as data “1”.

When one memory cell has three states (data “0”, data “1”, and data“2”), for example, as shown in FIG. 25, a state in which the bit lineoutput voltage in a read operation becomes 3.5 to 4.5 V (thresholdvoltage of about −2.5 V to −1.5 V) may be set as data “0” (erasedstate), a state in which the bit line output voltage becomes 1.5 to 2.5V (threshold voltage of about −0.5 to 0.5 V) may be set as data “1”, anda state in which the bit line output voltage becomes 0 to 0.5 V(threshold voltage of about 1.5 to 2.5 V) may be set as data “2”.

FIG. 26 shows a memory cell array 1 of a NOR-cell EEPROM according tothe fourth embodiment of the present invention. The memory cell array 1is formed on a p-type well or a p-type substrate, and each memory cell Mis arranged between a bit line BL and a common source line Vs. Eachmemory cell has a floating gate and a word line WL which are stacked andformed on each other.

The threshold voltages of the memory cells are read out as shown inFIGS. 27A and 27B. Voltages are applied as shown in FIG. 27A, and thebit line BL is set in a floating state. When the bit line BL is reset to0 V in advance, the bit line BL is charged by the common source line Vsthrough the memory cell. The potential of the charged bit line BL isdetermined by the threshold voltage of selected memory cell M.

In this embodiment, the word line WL is set to be 6 V, and the commonsource line Vs is set to be 6 V. The voltage waveforms of these partsare shown in FIG. 27B. In this manner, a threshold voltage of 0 to 6 Vcan be read out. When the potential of the bit line BL is 0 V, athreshold voltage of 6 V or more can be read out; when the bit linepotential is 6 V, a threshold voltage of 0 V or less can be read out.The relationship between the threshold voltage of the memory cell and abit line output voltage in this case is shown in FIG. 28. When acalculation is performed on the basis of a threshold voltage at a backbias voltage of 0 V, a solid line in FIG. 28 is obtained. However, as inFIG. 22, the bit line voltage becomes equal to the back bias voltage inpractice, and the bit line output voltage decreases as indicated by achain line in FIG. 28.

After electrons are injected into the floating gate of the memory cellby an erase operation, the electrons are discharged from the floatinggate by a write operation performed according to write data. FIG. 29shows the relationship between a write time and a bit line outputvoltage in a read operation. For example, in the case of the voltage ofthe common source line in the read operation is 3 V, when the thresholdvoltage becomes 3 V or less according to electron discharge from thefloating gate, the bit line output voltage does not change. Even whenthe voltage of the common source line is 6 V, the bit line outputvoltage in the read operation does not change at the threshold voltageof 0 V or less.

When one memory cell has two states (data “0” and data “1”), forexample, as shown in FIG. 30, a state in which the bit line outputvoltage in a read operation becomes 1 to 2 V (threshold voltage of about4 V to 5 V) may be set as data “0” (erased state), and a state in whichthe bit line output voltage becomes 3 to 4 V (threshold voltage of about2 to 3 V) may be set as data “1”.

When one memory cell has three states (data “0”, data “1”, and data“2”), for example, as shown in FIG. 31, a state in which the bit lineoutput voltage in a read operation becomes 0 to 0.5 V (threshold voltageof about 5.5 V or more) may be set as data “0” (erased state), a statein which the bit line output voltage becomes 1.5 to 2.5 V (thresholdvoltage of about 3.5 to 4.5 V) may be set as data “1”, and a state inwhich the bit line output voltage becomes 3.5 to 4.5 V (thresholdvoltage of about 1.5 to 2.5 V) may be set as data “2”.

FIG. 32 shows the arrangement of a ternary storage type EEPROM accordingto the third and fourth embodiments of the present invention. For memorycell arrays 1 ((a) and (b)), a bit line control circuit 2 forcontrolling a bit line in read/write operations and a word line drivecircuit 7 for controlling a word line potential are arranged. The bitline control circuit 2 is selected by a column decoder 3. The bit linecontrol circuit 2 receives and outputs read/write data from/to aninput/output data conversion circuit 5 through a data input/output line(IO line). The input/output data con10 version circuit 5 convertsmultivalue information of a readout memory cell into binary informationto externally output the multivalue information, and converts the binaryinformation of external input write data into the multivalue informationof a memory cell. The input/output data conversion circuit 5 isconnected to a data input/output buffer 6 for controlling a datainput/output operation with an external circuit.

FIG. 33 shows the detailed arrangements of a memory cell array 1 and abit line control circuit 2 in a NAND-cell EEPROM according to the thirdembodiment of the present invention. One terminal of the NAND cell isconnected to a bit line BL, and the other terminal is connected to acommon source line Vs. Selection gates SG1 and SG2 and control gates CG1to CG8 are shared by a plurality of NAND cells, and memory cells M whichshare one control gate constitute a page. Each of the memory cells Mstores data at a threshold voltage Vt thereof. As shown in FIG. 25, thememory cell stores data “0”, data “1”, and data “2”. One memory cell hasthree states, and nine combinations can be obtained by two memory cells.Of these nine combinations, eight combinations are used, and data ofthree bits are stored in the two memory cells.

In this embodiment, data of three bits are stored in a pair of adjacentmemory cells which share a control gate. In addition, the memory cellarrays 1 ((a) and (b)) are formed on dedicated p-type wells,respectively.

N-channel MOS transistors (n-ch Trs.) Qn8 to Qn10 and p-channel MOStransistors (p-ch Trs.) Qp3 to Qp5 constitute a flip-flop FF1, and n-chTrs. Qn11 to Qn13 and p-ch Trs. Qp6 to Qp8 constitute a flip-flop FF2.These flip-flops latch write/read data. The flip-flops are also operatedas sense amplifiers. The flip-flop FF1 latches write data informationindicating whether data “0” or data “1” or “2” is to be written, andlatches read data information indicating whether a memory cell storesthe information of data “0” or the information of data “1” or “2”. Theflip-flop FF2 latches write data information indicating whether data “1”or “2” is to be written, and latches read data information indicatingwhether a memory cell stores the information of data “2” or theinformation of data “0” or “1”.

An n-ch Tr. Qn1 transfers a voltage Va to a bit line BLa when aprecharge signal φpa goes to “H” level. an n-ch Tr. Qn20 transfers avoltage Vb to a bit line BLb when a precharge signal φpb goes to “H”level. N-ch Trs. Qn4 to Qn7 and p-ch Trs. Qp1 and Qp2 selectivelytransfer voltages VBHa, VBMa, and VBLa to the bit line BLa in accordancewith the data latched in the flip-flops FF1 and FF2. N-ch Trs. Qnt4 toQn17 and p-ch Trs. Qp9 and Qp10 selectively transfer voltages VBHb,VBMb, and VBLb to the bit line BLb in accordance with the data latchedin the flip-flops FF1 and FF2. An n-ch Tr. Qn2 connects the flip-flopFF1 to the bit line BLa when a signal φa1 goes to “H” level. An n-ch TrQn3 connects the flip-flop FF2 to the bit line BLa when a signal φa2goes to “H”. An n-ch Tr. Qn19 connects the flip-flop FF1 to the bit lineBLb when a signal φb1 goes to “H” level. An n-ch Tr. Qn18 connects theflip-flop FF2 to the bit line BLb when a signal φb2 goes to “H” level.

The operation of the EEPROM arranged as described above will bedescribed below with reference to FIGS. 34 to 36. FIG. 34 shows readoperation timings, FIG. 35 shows write operation timings, and FIG. 36shows verify read operation timings. FIGS. 34 to 36 show timingsobtained when a control gate CG2a is selected.

The read operation is executed by two basic cycles. In the first readcycle, the voltage Vb is set to be 3 V, and the bit line BLb serving asa dummy bit line is precharged. The precharge signal φpa goes to “L”level to cause the bit line BLa to float, and a common source line Vsais set to be 6 V. Subsequently, selection gates SG1a and SG2a andcontrol gates CG1a and CG3a to CG8a are set to be 6 V. At the same time,the selected control gate CG2a is set to be 2 V. Only when data “0” iswritten in the selected memory cell, the voltage of the bit line BLa isset to be 3 V or more.

Thereafter, flip-flop activation signals φn1 and φp1 go to “L” level and“H” level, respectively, to reset the flip-flop FF1. The signals φa1 andφb1 go to “H” level to connect the flip-flop FF1 to the bit lines BLaand BLb. The signals φn1 and φp1 go to “H” level and “L” level,respectively, to sense a bit line potential, and the flip-flop FF1latches the information of data “0” or the information of data “1” or“2”.

In the second read cycle, unlike the first read cycle, the voltage ofthe dummy bit line BLb is not 3 V but is 1 V, and signals φa2, φb2, φn2,and φp2 are output in place of the signals φa1, φb1, φn1, and φp1.Therefore, in the second read cycle, the flip-flop FF2 latches theinformation of data “2” or the information of data “1” or “0”.

With the two read cycles described above, the data written in the memorycells are read out.

Data in the memory cells are erased prior to a data write operation, andthe threshold voltages Vt of the memory cells are set to be −1.5 V orless. The common source line Vsa and the selection gates SG1a and SG2aare set to be 20 V, and the control gates CG1a to CG8a are set to be 0V, thereby performing an erase operation.

In the write operation, the precharge signal φpa goes to “L” level tocause the bit line BLa to float. The selection gate SG1a is set to beVcc, and the control gates CG1a to CG8a are set to be Vcc. The selectiongate SG2a is set to be 0 V during the write operation. At the same time,a signal VRFYa goes to “H” level, and a signal PBa goes to “L” level. Ina “0”-data write operation, since the flip-flop FF1 latches data suchthat the potential of a node N1 goes to “L” level, the bit line BLa ischarged to Vcc by the voltage VBHa. In a “1”- or “2”-data writeoperation, the bit line BLa is set to be 0 V.

Subsequently, the selection gate SGla and the control gates CG1a to CG8aare set to be 10 V, the voltage VBHa and a voltage vrw are set to be 8V, and the voltage VBMa is set to be 1 V. In the “1”-data writeoperation, since the flip-flop FF2 latches data such that the potentialof a node N3 goes to “L” level, a voltage of 1 V is applied to the bitline BLa by the voltage VBMa. The bit line BLa is set to be 0 V in the“2”-data write operation, and bit line BLa is set to be 8 V in the“0”-data write operation. Thereafter, the selected control gate CG2a isset to be 20 V.

In the “1”- or “2”-data write operation, electrons are injected into thecharge accumulation layers of the memory cells by the potentialdifference between the bit line BLa and the control gate CG2a, and thethreshold voltages of the memory cells increase. In a “1”-data writeoperation, since amounts of charges to be injected into the chargeaccumulation layers of the memory cells in the “1”-data write operationmust be smaller than those in the “2”-data write operation, the bit lineBLa is set to be 1 V to relax the potential difference between the bitline BLa and the control gate CG2a to 19 V. In the “0”-data writeoperation, the threshold voltages of the memory cells do not effectivelychange according to the bit line voltage of 8 V.

Upon completion of the write operation, the selection gate SG1a and thecontrol gates CG1a to CG8a are set to be 0 V, and then the voltage ofthe bit line BLa set to be 8 V in the “0”-data write operation is resetto 0 V with a time lag. This is because, when the order of the resettingoperations is reversed, a “2”-data write operation state is temporarilyset, and erroneous data is written in the “0”-data write operation.

After the write operation, a verify read operation is performed to checkthe written state of the memory cell and perform an additional writeoperation to only a memory cell in which data is not sufficientlywritten.

The verify read operation is similar to the first read cycle except thatthe data of the flip-flop FF1 is inverted, the voltage Vb is set to beVcc, the signal VRFYa and a signal VRFYb are output, and at this time,the voltages VBLb and VBMb are set to be 2.5 V and 0.5 V, respectively.The voltage of the bit line BLb is determined by the voltages Vb, VBLb,and VBMb and the data of the flip-flops FF1 and FF2. The signals VRFYaand VRFYb are output before the signals φn1 and φp1 go to “L” level and“H” level, respectively, after the selection gates SG1a and SG2a and thecontrol gates CG1a to CG8a are reset to 0 V. In other words, the signalsVRFYa and VRFYb are output before the flip-flop FF1 is reset after thepotential of the bit line BLa is determined by the threshold voltage ofthe memory cell.

The inverting operation of the data of the flip-flop FF1 will bedescribed below. The voltage Vb is set to be 2.5 V to precharge the bitline BLb serving as a dummy bit line. In addition, the precharge signalφpa and φpb go to “L” level to cause the bit lines BLa and BLb to float.Subsequently, the signal PBa goes to “L” level, and the bit line BLa ischarged to 2.5 V or more only when the potential of the node N1 is setat “L” level. Thereafter, the flip-flop activation signals φn1 and φp1go to “L” level and “H” level, respectively, to reset the flip-flop FF1.The signals φa1 and φb1 go to “H” level to connect the flip-flop FF1 tothe bit lines BLa and BLb, and the signals φn1 and φp1 go to “H” leveland “L” level, respectively, to sense a bit line potential. By thisoperation, the data of the flip-flop FF1 is inverted.

The data (data 1) latched in the flip-flop FF1, the data (data 2)latched in the flip-flop FF2, and the voltages of the bit lines BLa andBLb determined by the threshold voltage of a selected memory cell andobtained after the data inverting operation will be described below. Thedata 1 controls “0”-data write operation or “1”- or “2”-data writeoperation. In the “0”-data write operation, the potential of the node N1goes to “H” level set upon the data inverting operation. In the “1”- or“2”-data write operation, the potential of the node N1 goes to “L” levelset upon the data inverting operation. The data 2 controls “1”-datawrite operation or “2”-data write operation. The potential of the nodeN3 goes to “L” level in the “1”-data write operation, and the potentialof the node N3 goes to “H” level in the “2”-data write operation.

In the verify read operation performed after the “0”-data writeoperation, regardless of the states of the memory cells, when the signalVRFYa goes to “H” level, the voltage VBLa or VBMa causes the potentialof the bit line BLa to go to “L” level. Therefore, the bit line BLa issensed by the flip-flop FF1 such that the node N1 goes to “L” level, andrewrite data to be latched is data “0”.

In the verify read operation set upon the “1” data write operation, thesignal VRFYb goes to “H” level, and the dummy bit line BLb is set to be2.5 V. When the memory cell is not set in a “1”-data-written state, thevoltage of the bit line BLa is 2.5 V or more, and the bit line BLa issensed by the flip-flop FF1 such that the potential of the node N1 goesto “H” level, and rewrite data to be latched is data “1”. When thememory cell reaches the “1”-data-written state, the bit line BLa is 2.5V or less, the bit line BLa is sensed by the flip-flop FF1 such that thepotential of the node N1 goes to “L” level, and rewrite data to belatched is data “0”.

In the verify read operation performed after the “2”-data writeoperation, the signal VRFYb goes to “H” level to set the dummy bit lineBLb to be 0.5 V. When the memory cell does not reach a “2”-data-writtenstate, the voltage of the bit line BLa is 0.5 or more, the bit line BLais sensed by the flip-flop FF1 such that the potential of the node N1goes to “H” level, and rewrite data to be latched is data “2”. when thememory cell reaches the “2”-data-written state, the voltage of the bitline BLa is 0.5 V or less, the bit line BLa is sensed by the flip-flopFF1 such that the potential of the node N1 goes to “L” level, andrewrite data to be latched is data “0”.

With this verify read operation, rewrite data is set as described in thefollowing table (Table 6) on the basis of write data and the writtenstate of the memory cell.

TABLE 6 Write Data 0 0 0 1 1 2 2 2 Memory Cell Data 0 1 2 0 1 0 1 2Rewrite Data 0 0 0 1 0 2 2 0

As is apparent from the table (Table 6), although the “1”-data-writtenstate is to be set, data “1” is written again in only a memory cell inwhich data “1” is not sufficiently written. Although the“2”-data-written state is to be set, data “2” is written again in only amemory cell in which data “2” is not sufficiently written.

The write operation and the verify read operation are repeatedlyperformed, thereby performing a data write operation.

The following table (Table 7) shows the potentials at the several pointsof the memory cell array in an erase operation, a write operation, aread operation, and a verify read operation.

TABLE 7 Write Erase Operation Read Operation Verify Read Operation “0”“1” “2” First Cycle Second Cycle Operation BLa 20 V  8 V  1 V 0 V “H”only when “L” only when See FIG. 36 data “2” is read data “2” is readSG1a 20 V  10 V 6 V 6 V 6 V CG1a 0 V 10 V 6 V 6 V 6 V CG2a 0 V 20 V 2 V2 V 2 V CG3a 0 V 10 V 6 V 6 V 6 V CG4a 0 V 10 V 6 V 6 V 6 V CG5a 0 V 10V 6 V 6 V 6 V CG6a 0 V 10 V 6 V 6 V 6 V CG7a 0 V 10 V 6 V 6 V 6 V CG8a 0V 10 V 6 V 6 V 6 V SG2a 20 V   0 V 6 V 6 V 6 V Vsa 20 V   0 V 6 V 6 V 6V P well 20 V   0 V 0 V 0 V 0 V

FIG. 37 shows the detailed arrangement of a memory cell array and a bitline control circuit 2 in a NOR-cell EEPROM according to the fourthembodiment of the present invention. One terminal of a NOR cell isconnected to a bit line BL, and the other terminal is connected to acommon source line Vs. A word line WL is shared by a plurality of NORcells, and memory cells M which share one word line constitute a page.Each memory cell stores data by using a threshold voltage Vt of thecorresponding memory cell, and as shown in FIG. 31, stores data “0”,data “1”, and data “2”. One memory cell has three states, and ninecombinations can be obtained by two memory cells. Of these ninecombinations, eight combinations are used, and data of three bits arestored in the two memory cells. In this embodiment, data of three bitsare stored in a pair of adjacent memory cells which share a word line.In addition, the memory cell arrays 1 ((a) and (b)) are formed on ap-type substrate.

N-ch Trs. Qn26 to Qn28 and p-ch Trs. Qp15 to Qp17 constitute a flip-flopFF3, and n-ch Trs. Qn29 to Qn31 and p-ch Trs. Qp18 to Qp20 constitute aflip-flop FF4. These flip-flops latch write/read data. The flip-flopsare also operated as sense amplifiers. The flip-flop FF3 latches writedata information indicating whether data “0” or data “1” or “2” is to bewritten, and latches read data information indicating whether a memorycell stores the information of data “0” or the information of data “1”or “2”. The flip-flop FF4 latches write data information indictingwhether data “1” or “2” is to be written, and latches read datainformation indicating whether a memory cell stores the information ofdata “2” or the information of data “0” or “1”.

An n-ch Tr. Qn21 transfers a voltage Va to a bit line BLa when aprecharge signal φpa goes to “H” level. An n-ch Tr. Qn36 transfers avoltage Vb to a bit line BLb when a precharge signal φpb goes to “H”level. N-ch Trs. Qn24 and Qn25 and p-ch Trs. Qp11 to Qp14 selectivelytransfer voltages VBHa and VBMa and a voltage of 0 V to the bit line BLain accordance with the data latched in the flip-flops FF3 and FF4. N-chTrs. Qn32 and Qn33 and p-ch Trs. Qp21 to Qp24 selectively transfervoltages VBHb and VBMb and a voltage of 0 V to the bit line BLb inaccordance with the data latched in the flip-flops FF3 and FF4. An n-chTr. Qn22 connects the flip-flop FF3 to the bit line BLa when a signalφa1 goes to “H” level. An n-ch Tr Qn23 connects the flip-flop FF4 to thebit line BLa when a signal φa2 goes to “H” level. An n-ch Tr. Qn35connects the flip-flop FF3 to the bit line BLb when a signal φb1 goes to“H” level. An n-ch Tr. Qn34 connects the flip-flop FF4 to the bit lineBLb when a signal φb2 goes to “H” level.

The operation of the EEPROM arranged as described above will bedescribed below with reference to FIGS. 38 to 40. FIG. 38 shows readoperation timings, FIG. 39 shows write operation timings, and FIG. 40shows verify read operation timings. FIGS. 38 to 40 show timingsobtained when a word line WLa is selected.

The read operation is executed by two basic cycles. In the first readcycle, the voltage Vb becomes 1 V to precharge the bit line BLb servingas a dummy bit line. The precharge signal φpa goes to “L” level to causethe bit line BLa to float, and a common source line Vsa is set to be 6V. Subsequently, the word line WLa is set to be 6 V. Only when data “0”is written in the selected memory cell, the voltage of the bit line BLais set to be 0.5 V or less.

Thereafter, flip-flop activation signals φn1 and φp1 go to “L” level and“H” level, respectively, to reset the flip-flop FF3. The signals φa1 andφb1 go to “H” level to connect the flip-flop FF3 to the bit lines BLaand BLb. The signals φn1 and φp1 go to “H” level and “L” level,respectively, to sense a bit line potential, and the flip-flop FF3latches the information of data “0” or the information of data “1” or“2”.

In the second read cycle, unlike the first read cycle, the voltage ofthe dummy bit line BLb is not 1 V but is 3 V, and signals φa2, φb2, φn2,and φp2 are output in place of the signals φa1, φb1, φn1, and φp1.Therefore, in the second read cycle, the flip-flop FF4 latches theinformation of data “2” or the information of data “1” or “0”.

With the two read cycles described above, the data written in the memorycells are read out.

Data in the memory cells are erased prior to a data write operation, andthe threshold voltages Vt of the memory cells are set to be 5.5 V ormore. The word line WLa is set to be 20 V, and the bit line BLa is setto be 0 V, thereby performing the erase operation. In the writeoperation, the precharge signal φpa goes to “L” level to cause the bitline BLa to float. Subsequently, a signal VRFYBa goes to “L” level, anda signal Pa goes to “H” level. In a “0”-data write operation, since theflip-flop FF3 latches data such that the potential of a node N5 goes to“H” level, the bit line BLa is set to be 0 V. In a “1”- or “2”-datawrite operation, the bit line BLa is set to be Vcc by the voltage VBHaor VBMa.

Subsequently, each of the voltage VBHa and a voltage Vrw becomes 8 V,and the voltage VBMa becomes 7 V. In the “1”-data write operation, sincethe flip-flop FF4 latches data such that the potential of node N7 goesto “H” level, a voltage of 7 V is applied to the bit line BLa by thevoltage VBMa. The bit line BLa is set to be 8 V in the “2”-data writeoperation, and bit line BLa is set to be 0 V in the “0”-data writeoperation. Thereafter, the selected word line WLa is set to be −12 V.

In the “1”- or “2”-data write operation, electrons are discharged fromthe charge accumulation layers of the memory cells by the potentialdifference between the bit line BLa and the word line WLa, and thethreshold voltages of the memory cells decrease. In a “1”-data writeoperation, since amounts of charges to be discharged from the chargeaccumulation layers of the memory cells in the “1”-data write operationmust be smaller than those in the “2”-data write operation, the bit lineBLa is set to be 7 V to relax the potential difference between the wordline WLa and the bit line BLa to 19 V. In the “0”-data write operation,the threshold voltage of the memory cell does not effectively changeaccording to the bit line voltage of 0 V

After the write operation, a verify read operation is performed to checkthe written state of the memory cells and perform an additional writeoperation to only a memory cell in which data is not sufficientlywritten.

The verify read operation is similar to the first read cycle except thatthe data of the flip-flop FF3 is inverted, the voltage Vb is 0 V, thesignal VRFYBa and a signal VRFYBb are output, and at this time, thevoltages VBHb and VBMb become 1.5 V and 3.5 V, respectively. The voltageof the bit line BLb is determined by the voltages Vb, VBHb, and VBMb andthe data of the flip-flops FF3 and FF4. The signals VRFYBa and VRFYBbare output before the signals φn1 and φp1 go to “L” level and “H” level,respectively, after the word line WLa is reset to 0 V. In other words,the signals VRFYBa and VRFYBb are output before the flip-flop FF3 isreset after the potential of the bit line BLa is determined by thethreshold voltages of the memory cells.

The inverting operation of the data of the flip-flop FF3 will bedescribed below. The voltages Va and Vb become Vcc and 2.5 V,respectively, to precharge the bit lines BLa and BLb. In addition, theprecharge signals φpa and φpb go to “L” level to cause the bit lines BLaand BLb to float. Subsequently, the signal Pa goes to “H” level, and thebit line BLa is discharged to 2.5 V or less only when the potential ofthe node N5 is set at “H” level. Thereafter, the flip-flop activationsignals φn1 and φp1 go to “L” level and “H” level, respectively, toreset the flip-flop FF3, the signals φa1 and φb1 go to “H” level toconnect the flip-flop FF3 to the bit lines BLa and BLb, and the signalsφn1 and φp1 go to “H” level and “L” level, respectively, to sense a bitline potential. With this operation, the data of the flip-flop FF3 isinverted.

The data (data 1) latched in the flip-flop FF3, the data (data 2)latched in the flip-flop FF4, and the voltages of the bit lines BLa andBLb determined by the threshold voltage of a selected memory cell andobtained after the data inverting operation will be described below. Thedata 1 controls “0”-data write operation or “1”- or “2”-data writeoperation. In the “0”-data write operation, the potential of the node N5goes to “L” level set upon the data inverting operation. In the “1”- or“2”-data write operation, the potential of the node N5 goes to “H” levelset upon the data inverting operation. The data 2 controls “1”-datawrite operation or “2”-data write operation. The potential of the nodeN7 goes to “H” level in the “1”-data write operation, and the potentialof the node N7 goes to “L” level in the “2”-data write operation.

In the verify read operation performed after the “0”-data writeoperation, regardless of the states of the memory cells, when the signalVRFYBa goes to “L” level, the voltage VBHa or VBMa causes the potentialof the bit line BLa to go to “H” level. Therefore, the bit line BLa issensed by the flip-flop FF3 such that the node N5 goes to “H” level, andrewrite data to be latched is data “0”.

In the verify read operation after the “1” data write operation, thesignal VRFYBb goes to “L” level to set the dummy bit line BLb to be 1.5V. Therefore, when the memory cell does not reach a “1”-data-writtenstate, the bit line BLa is set to be 1.5 V or less, the bit line BLa issensed by the flip-flop FF3 such that the potential of the node N5 goesto “L” level, and rewrite data to be latched is data “1”. When thememory cell reaches the “1”-data-written state, the bit line BLa is setto be 1.5 V or more, the bit line BLa is sensed by the flip-flop FF3such that the potential of the node N5 goes to “H” level, and rewritedata to be latched is data “0”.

In the verify read operation performed after the “2”-data writeoperation, the signal VRFYBb goes to “L” level to set the dummy bit lineBLb to be 3.5 V. Therefore, when the memory cell does not reach a“2”-data-written state, the bit line BLa is set to be 3.5 or less, thebit line BLa is sensed by the flip-flop FF3 such that the potential ofthe node N5 goes to “L” level, and rewrite data to be latched is data“2”. When the memory cell reaches the “2”-data-written state, the bitline BLa is set to be 3.5 V or more, the bit line BLa is sensed by theflip-flop FF3 such that the potential of the node N5 goes to “H” level,and rewrite data to be latched is data “0”.

With this verify read operation, rewrite data is set as described in theabove Table 6 on the basis of write data and the written states of thememory cells. As is apparent from the Table 6, although the“1”-data-written state is to be set, data “1” is written again in only amemory cell in which data “1” is not sufficiently written. Although the“2”-data-written state is to be set, data “2” is written again in only amemory cell in which data “2” is not sufficiently written.

The write operation and the verify read operation are repeatedlyperformed, thereby performing a data write operation.

The following table (Table 8) shows the potentials at BLa, WLa and Vsaof the memory cell array in an erase operation, a write operation, aread operation, and a verify read operation.

TABLE 8 Write Erase Operation Read Operation Verify Read Operation “0”“1” “2” First Cycle Second Cycle Operation RLa 0 V 0 V  7 V 8 V “L” onlywhen “H” only when See FIG. 40 data “2” is read data “2” is read WLa 20V  −12 V 6 V 6 V 5 V Vsa 0 V  0 V 6 V 6 V 6 V

FIG. 41 shows a circuit for controlling data input/output operationsbetween the flip-flops FF1 and FF2 shown in FIG. 33 or the flip-flopsFF3 and FF4 shown in FIG. 37 and the input/output data conversioncircuit shown in FIG. 32. An inverter I₁ and a NAND circuit G₁constitute a column decoder 3. When a column activation signal CENB goesto “H” level, a decoder output selected by an address signal goes to “H”level, and nodes A, B, C, and D are connected to input/output linesIOA1, IOB1, IOA2, and IOB2, respectively. The nodes A, B, C, and Dcorrespond to the nodes N1, N2, N3, and N4 in FIG. 33, respectively, andcorrespond to the nodes N6, N5, N8, and N7 in FIG. 37, respectively. Therelationships between read/write data and the input/output lines IOA1,IOB1, IOA2, and IOB2 are summarized in the following table (Table 9).

TABLE 9 Write Data IOA1 IOB1 IOA2 IOB2 0 L H — — 1 H L L H 2 H L H L (a)

TABLE 9 Read Data IOA1 IOB1 IOA2 IOB2 0 H L H L 1 L H H L 2 L H L H (b)

As has been described above, according to the present invention, whilean increase in circuit area is suppressed, three written states are setin one memory cell, and write times required for setting written statesin memory cells are independently made optimum by write verify control,thereby obtaining an EEPROM capable of controlling the threshold voltagedistribution of each memory cell in which data is finally written tofall within a small range at a high speed. In addition, when two, four,or more written states are set in one memory cell, the same effect asdescribed above can be obtained according to the purport and scope ofthe present invention.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details, and representative devices shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A multi-level non-volatile semiconductor memory device comprising: asemiconductor substrate; a plurality of bit lines; a plurality of wordlines insulatively intersecting said bit lines; a memory cell arraycomprising a plurality of memory cells coupled to said word lines andbit lines, each memory cell including a transistor with a charge storageportion and having written states of first, second, . . . , (n−1)th andnth (n≧3) predetermined storage levels; a plurality of programmingcontrol circuits coupled to said memory cell array for storing data offirst, second, . . . , (n−1)th and nth predetermined logic levels indata storage portions which define write voltages to be applied torespective of said memory cells, for applying said write voltages tosaid respective of said memory cells according to the data stored insaid data storage portions, for determining actual written states ofsaid memory cells, for modifying stored data from said ith (i=2, 3, . .. , n−1, n) predetermined logic level to said first predetermined logiclevel in the data storage portions storing the data of said ith(respectively, i=2, 3, . . . , n−1, n) predetermined logic level andcorresponding to the memory cells in which successful writing of saidith (respectively, i=2, 3, . . . , n−1, n) predetermined storage levelhas been determined, for maintaining said stored data at said ith (i=2,3, . . . , n−1, n) predetermined logic level in the data storageportions storing the data of said ith (respectively, i=2, 3, . . . ,n−1, n) predetermined logic level and corresponding to the memory cellsin which it has been determined that said ith (respectively, i=2, 3, . .. , n−1, n) predetermined storage level has not been successfullywritten, and for maintaining said stored data at said firstpredetermined logic level in the data storage portions storing the dataof said first predetermined logic level.
 2. The device according toclaim 1, wherein said data stored in said data storage portions areinitially set to initial data, and then said initial data stored in saiddata storage portions are modified.
 3. The device according to claim 2,wherein said initial data are loaded from at least one input linecoupled to said data storage portions.
 4. The device according to claim1, wherein said actual written states of said memory cells correspondingto the data storage portions storing the data of said ith (i=2, 3, . . ., n−1, n) predetermined logic level are simultaneously determined. 5.The device according to claim 1, wherein said actual written states ofsaid memory cells corresponding to the data storage portions storing thedata of said second, third, . . . , (n−1))th and nth predetermined logiclevels are simultaneously determined.
 6. The device according to claim1, wherein said data of said ith (i=2, 3, . . . , n−1, n) predeterminedlogic level stored in the data storage portions corresponding to thememory cells in which successful writing has been determined aresimultaneously modified to the data of said first predetermined logiclevel.
 7. The device according to claim 1, wherein said data of saidsecond, third, . . . , (n−1)th and nth predetermined logic levels storedin the data storage portions corresponding to the memory cells in whichsuccessful writing has been determined are simultaneously modified tothe data of said first predetermined logic level.
 8. The deviceaccording to claim 1, further comprising a plurality of data write enddetection circuits coupled to said data storage portions forsimultaneously detecting whether or not all of said data storageportions store the data of said first predetermined logic level.
 9. Thedevice according to claim 8, wherein each of said data write enddetection circuits is provided for each of said data storage portions.10. The device according to claim 9, wherein said data write enddetection circuits are coupled to at least one common output line, andsaid data write end detection circuits output a programming completionsignal on said common output line when each data storage portion storesthe data of said first predetermined logic level.
 11. The deviceaccording to claim 10, wherein said applying, determining and modifyingare continued until said data write end detection circuits output saidprogramming completion signal.
 12. The device according to claim 1,wherein said applying, determining and modifying are continued untileach memory cell is sufficiently written.
 13. The device according toclaim 1, wherein said write voltages are simultaneously applied to saidrespective of said memory cells.
 14. The device according to claim 13,wherein said write voltages defined by said data stored in said datastorage portions and applied to said respective of said memory cellsdiffer according to said data stored in said data storage portions. 15.The device according to claim 1, wherein said programming controlcircuits are arranged adjacent to said memory cell array.
 16. The deviceaccording to claim 1, wherein each of said programming control circuitsis connected to a respective one of said bit lines.
 17. The deviceaccording to claim 1, wherein said programming control circuits includebit line voltage regulators for selectively changing voltages of saidbit lines according to said data stored in said data storage portions.18. The device according to claim 17, wherein said voltages of said bitlines are selectively and simultaneously changed by said bit linevoltage regulators.
 19. A multi-value non-volatile semiconductor memorydevice comprising: a semiconductor substrate; a plurality of bit lines;a plurality of word lines insulatively intersecting said bit lines; amemory cell array comprising a plurality of memory cells coupled to saidword lines and bit lines, each memory cell including a transistor with acharge storage portion and having written states of first, second, . . ., (n−1)th and nth (n≧3) predetermined storage levels; a plurality ofprogramming control circuits coupled to said memory cell array forstoring data of first, second, . . . , (n−1)th and nth predeterminedlogic levels in data storage portions which define write voltages to beapplied to respective of said memory cells, said data being initiallyset to initial data which are loaded from at least one input linecoupled to said data storage portions, for applying said write voltagesto said respective of said memory cells according to the data stored insaid data storage portions, for determining actual written states ofsaid memory cells, for modifying stored data from said ith (i=2, 3, . .. , n−1, n) predetermined logic level to said first predetermined logiclevel in the data storage portions storing the data of said ith(respectively, i=2, 3, . . . , n−1, n) predetermined logic level andcorresponding to the memory cells in which successful writing of saidith (respectively, i=2, 3, . . . , n−1, n) predetermined storage levelhas been determined, for maintaining said stored data at said ith (i=2,3, . . . , n−1, n) predetermined logic level in the data storageportions storing the data of said ith (respectively, i=2, 3, . . . ,n−1, n) predetermined logic level and corresponding to the memory cellsin which it has been determined that said ith (respectively, i=2, 3, . .. , n−1, n) predetermined storage level has not been successfullywritten, and for maintaining said stored data at said firstpredetermined logic level in the data storage portions storing the dataof said first predetermined logic level.
 20. The device according toclaim 19, wherein said actual written states of said memory cellscorresponding to the data storage portions storing the data of said ith(i=2, 3, . . . , n−1, n) predetermined logic level are simultaneouslydetermined.
 21. The device according to claim 19, wherein said actualwritten states of said memory cells corresponding to the data storageportions storing the data of said second, third, . . . , (n−1)th and nthpredetermined logic levels are simultaneously determined.
 22. The deviceaccording to claim 19, wherein said data of said ith (i=2, 3, . . . ,n−1, n) predetermined logic level stored in the data storage portionscorresponding to the memory cells in which successful writing has beendetermined are simultaneously modified to the data of said firstpredetermined logic level.
 23. The device according to claim 19, whereinsaid data of said second, third, . . . , (n−1)th and nth predeterminedlogic levels stored in the data storage portions corresponding to thememory cells in which successful writing has been determined aresimultaneously modified to the data of said first predetermined logiclevel.
 24. The device according to claim 19, further comprising aplurality of data write end detection circuits coupled to said datastorage portions for simultaneously detecting whether or not all of saiddata storage portions store the data of said first predetermined logiclevel.
 25. The device according to claim 24, wherein each of said datawrite end detection circuits is provided for each of said data storageportions.
 26. The device according to claim 25, wherein said data writeend detection circuits are coupled to at least one common output line,and said data write end detection circuits output a programmingcompletion signal on said common output line when each data storageportion stores the data of said first predetermined logic level.
 27. Thedevice according to claim 26, wherein said applying, determining andmodifying are continued until said data write and detection circuitsoutput said programming completion signal.
 28. The device according toclaim 19, wherein said applying, determining and modifying are continueduntil each memory cell is sufficiently written.
 29. The device accordingto claim 19, wherein said write voltages are simultaneously applied tosaid respective of said memory cells.
 30. The device according to claim29, wherein said write voltages defined by said data stored in said datastorage portions and applied to said respective of said memory cellsdiffer according to said data stored in said data storage portions. 31.The device according to claim 19, wherein said programming controlcircuits are arranged adjacent to said memory cell array.
 32. The deviceaccording to claim 19, wherein each of said programming control circuitsis connected to a respective one of said bit lines.
 33. The deviceaccording to claim 19, wherein said programming control circuits includebit line voltage regulators for selectively changing voltages of saidbit lines according to said data stored in said data storage portions.34. The device according to claim 33, wherein said voltages of said bitlines are selectively and simultaneously changed by said bit linevoltage regulators.
 35. A multi-level non-volatile semiconductor memorydevice comprising: a semiconductor substrate; a plurality of bit lines;a plurality of word lines insulatively intersecting said bit lines; amemory cell array comprising a plurality of memory cells coupled to saidword lines and bit lines, each memory cell including a transistor with acharge storage portion and having written states of first, second, . . ., (n−1)th and nth (n≧3) predetermined storage levels; a plurality ofprogramming control circuits coupled to said memory cell array forstoring data of first, second, . . . , (n−1)th, and nth predeterminedlogic levels in data storage portions which define write voltages to beapplied to respective of said memory cells, said data being initiallyset to initial data which are loaded from at least one input linecoupled to said data storage portions, for applying said write voltagesto said respective of said memory cells according to the data stored insaid data storage portions, for determining actual written states ofsaid memory cells, for maintaining stored data of said firstpredetermined logic level in the data storage portions storing the dataof said first predetermined logic level, and for selectively modifyingsaid stored data to the data of said first predetermined logic level inonly data storage portions initially storing the initial data of saidith (i=2, 3, . . . , n−1, n) predetermined logic level and correspondingto the memory cells in which successful writing of said ith(respectively, i=2, 3, . . . , n−1, n) predetermined storage level hasbeen determined, such that only memory cells which are not sufficientlywritten have write voltages applied thereto which achieve the writtenstate predetermined by the initial data in the respective memory cellupon application of the write voltages to the respective memory cell.36. The device according to claim 35, wherein said actual written statesof said memory cells corresponding to the data storage portions storingthe data of said ith (i=2, 3, . . . , n−1, n) predetermined logic levelare simultaneously determined.
 37. The device according to claim 35,wherein said actual written states of said memory cells corresponding tothe data storage portions storing the data of said second, third, . . ., (n−1)th and nth predetermined logic levels are simultaneouslydetermined.
 38. The device according to claim 35, wherein said data ofsaid ith (i=2, 3, . . . , n−1, n) predetermined logic level stored inthe data storage portions corresponding to the memory cells in whichsuccessful writing has been determined are simultaneously andselectively modified to the data of said first predetermined logiclevel.
 39. The device according to claim 35, wherein said data of saidsecond, third, . . . , (n−1)th and nth predetermined logic levels storedin the data storage portions corresponding to the memory cells in whichsuccessful writing has been determined are simultaneously andselectively modified to the data of said first predetermined logiclevel.
 40. The device according to claim 35, further comprising aplurality of data write end detection circuits coupled to said datastorage portions for simultaneously detecting whether or not all of saiddata storage portions store the data of said first predetermined logiclevel.
 41. The device according to claim 40, wherein each of said datawrite end detection circuits is provided for each of said data storageportions.
 42. The device according to claim 41, wherein said data writeend detection circuits are coupled to at least one common output line,and said data write end detection circuits output a programmingcompletion signal on said common output line when each data storageportion stores the data of said first predetermined logic level.
 43. Thedevice according to claim 42, wherein said applying, determining andselective modifying are continued until said data write end detectioncircuits output said programming completion signal.
 44. The deviceaccording to claim 35, wherein said applying, determining and selectivemodifying are continued until each memory cell is sufficiently written.45. The device according to claim 35, wherein said write voltages aresimultaneously applied to said respective of said memory cells.
 46. Thedevice according to claim 45, wherein said write voltages defined bysaid data stored in said data storage portions and applied to saidrespective of said memory cells differ according to said data stored insaid data storage portions.
 47. The device according to claim 45,wherein said programming control circuits are arranged adjacent to saidmemory cell array.
 48. The device according to claim 35, wherein each ofsaid programming control circuits is connected to a respective one ofsaid bit lines.
 49. The device according to claim 35, wherein saidprogramming control circuits include bit line voltage regulators forselectively changing voltages of said bit lines according to said datastored in said data storage portions.
 50. The device according to claim49, wherein said voltages of said bit lines are selectively andsimultaneously changed by said bit line voltage regulators.
 51. Amulti-level non-volatile semiconductor memory device comprising: asemiconductor substrate; a plurality of bit lines; a plurality of wordlines insulatively intersecting said bit lines; a memory cell arraycomprising a plurality of memory cells coupled to said word lines andbit lines, each memory cell including a transistor with a charge storageportion and having written states of first, second, . . . (n−1)th andnth (n≧3) predetermined storage levels; a plurality of cell selectioncircuits coupled to said memory cell array for controlling selection ofmemory cells and application of write voltages to the selected memorycells; a plurality of data circuits coupled to said memory cell arrayfor storing write control data of first, second, . . . , (n−1)th, andnth predetermined logic levels which define write control voltages to beapplied to respective of said memory cells selected by said cellselection circuits, said write control data being initially set toinitial write control data which are loaded from at least one input linecoupled to said data circuits, for applying said write control voltagesto said respective of said memory cells, for selectively sensing actualwritten states of only those of said respective memory cellscorresponding to the data circuits in which the write control data ofsaid second, third, . . . , (n−1)th and nth predetermined logic levelsare stored, for maintaining stored write control data at said firstpredetermined logic level in the data circuits storing the write controldata of said first predetermined logic level, and for selectivelymodifying said stored write control data to the write control data ofsaid first predetermined logic level in only data circuits initiallystoring the initial write control data of said ith (i=2, 3, . . . , n−1,n) predetermined logic level and corresponding to the memory cells inwhich successful writing of said ith (respectively, i=2, 3, . . . , n−1,n) predetermined storage level has been sensed, such that only memorycells which are not sufficiently written have write control voltagesapplied thereto which achieve the written state predetermined by theinitial write control data in the respective memory cell uponapplication of the write control voltages to the respective memory cell.52. The device according to claim 51, wherein said actual written statesof said memory cells corresponding to the data circuits storing thewrite control data of said ith (i=2, 3, . . . , n−1, n) predeterminedlogic level are simultaneously sensed.
 53. The device according to claim51, wherein said actual written states of said memory cellscorresponding to the data circuits storing the write control data ofsaid second, third, . . . , (n−1)th and nth predetermined logic levelsare simultaneously sensed.
 54. The device according to claim 51, whereinsaid write control data of said ith (i=2, 3, . . . , n−1, n)predetermined logic level stored in the data circuits corresponding tothe memory cells in which successful writing has been sensed aresimultaneously and selectively modified to the write control data ofsaid first predetermined logic level.
 55. The device according to claim51, wherein said write control data of said second, third, . . . (n−1)thand nth predetermined logic levels stored in the data circuitscorresponding to the memory cells in which successful writing has beensensed are simultaneously and selectively modified to the write controldata of said first predetermined logic level.
 56. The device accordingto claim 51, further comprising a plurality of data write end detectioncircuits coupled to said data circuits for simultaneously detectingwhether or not all of said data circuits store the write control data ofsaid first predetermined logic level.
 57. The device according to claim56, wherein each of said data write end detection circuits is providedfor each of said data circuits.
 58. The device according to claim 57,wherein said data write end detection circuits are coupled to at leastone common output line, and said data write end detection circuitsoutput a programming completion signal on said common output line wheneach data circuit stores the write control data of said firstpredetermined logic level.
 59. The device according to claim 58, whereinsaid applying, selective sensing and selective modifying are continueduntil said data write end detection circuits output said programmingcompletion signal.
 60. The device according to claim 51, wherein saidapplying, selective sensing and selective modifying are continued untileach memory cell is sufficiently written.
 61. The device according toclaim 51, wherein said write control voltages are simultaneously appliedto said respective of said memory cells.
 62. The device according toclaim 61, wherein said write control voltages defined by said writecontrol data stored in said data circuits and applied to said respectiveof said memory cells differ according to said write control data storedin said data circuits.
 63. The device according to claim 51, whereinsaid data circuits are arranged adjacent to said memory cell array. 64.The device according to claim 51, wherein each of said data circuits isconnected to a respective one of said bit lines.
 65. The deviceaccording to claim 51, wherein said data circuits include bit linevoltage regulators for selectively changing voltages of said bit linesaccording to said write control data stored in said data circuits. 66.The device according to claim 65, wherein said voltages of said bitlines are selectively and simultaneously changed by said bit linevoltage regulators.
 67. A multi-level non-volatile semiconductor memorydevice comprising: a semiconductor substrate; a plurality of bit lines;a plurality of word lines insulatively intersecting said bit lines; amemory cell array comprising a plurality of memory cells coupled to saidword lines and bit lines, each memory cell including a transistor with acharge storage portion and having written states of first, second, . . ., (n−1)th and nth (n≧3) predetermined storage levels; a plurality ofcell selection circuits coupled to said memory cell array forcontrolling selection of memory cells and application of write voltagesto the selected memory cells; a plurality of data circuits coupled tosaid memory cell array for storing write control data of first, second,. . . , (n−1)th, and nth predetermined logic levels which define writecontrol voltages to be applied to respective of said memory cellsselected by said cell selection circuits, for applying said writecontrol voltages to said respective of said memory cells, forselectively sensing actual written states of only those of saidrespective memory cells corresponding to the data circuits in which thewrite control data of said second, third, . . . , (n−1)th and nthpredetermined logic levels are stored, for modifying stored writecontrol data from said ith (i=2, 3, . . . , n−1, n) predetermined logiclevel to said first predetermined logic level in the data circuitsstoring the write control data of said ith (respectively, i=2, 3, . . ., n−1, n) predetermined logic level and corresponding to the memorycells in which successful writing of said ith (respectively, i=2, 3, . .. , n−1, n) predetermined storage level has been sensed, for maintainingsaid stored write control data at said ith (i=2, 3, . . . , n−1, n)predetermined logic level in the data circuits storing the write controldata of said ith (respectively, i=2, 3, . . . , n−1, n) predeterminedlogic level and corresponding to the memory cells in which it has beensensed that said ith (respectively, i=2, 3, . . . , n−1, n)predetermined storage level has not been successfully written, and formaintaining said stored write control data at said first predeterminedlogic level in the data circuits storing the write control data of saidfirst predetermined logic level.
 68. The device according to claim 67,wherein said write control data stored in said data circuits areinitially set to initial write control data, and then said initial writecontrol data stored in said data circuits are modified.
 69. The deviceaccording to claim 68, wherein said initial write control data areloaded from at least one input line coupled to said data circuits. 70.The device according to claim 67, wherein said actual written states ofsaid memory cells corresponding to the data circuits storing the writecontrol data of said ith (i=2, 3, . . . , n−1, n) predetermined logiclevel are simultaneously sensed.
 71. The device according to claim 67,wherein said actual written states of said memory cells corresponding tothe data circuits storing the write control data of said second, third,. . . , (n−1)th and nth predetermined logic levels are simultaneouslysensed.
 72. The device according to claim 67, wherein said write controldata of said ith (i=2, 3, . . . , n−1, n) predetermined logic levelstored in the data circuits corresponding to the memory cells in whichsuccessful writing has been sensed are simultaneously modified to thewrite control data of said first predetermined logic level.
 73. Thedevice according to claim 67, wherein said write control data of saidsecond, third, . . . , (n−1)th and nth predetermined logic levels storedin the data circuits corresponding to the memory cells in whichsuccessful writing has been sensed are simultaneously modified to thewrite control data of said first predetermined logic level.
 74. Thedevice according to claim 67, further comprising a plurality of datawrite end detection circuits coupled to said data circuits forsimultaneously detecting whether or not all of said data circuits storethe write control data of said first predetermined logic level.
 75. Thedevice according to claim 74, wherein each of said data write enddetection circuits is provided for each of said data circuits.
 76. Thedevice according to claim 75, wherein said data write end detectioncircuits are coupled to at least one common output line, and said datawrite end detection circuits output a programming completion signal onsaid common output line when each data circuit stores the write controldata of said first predetermined logic level.
 77. The device accordingto claim 76, wherein said applying, selective sensing and modifying arecontinued until said data write end detection circuits output saidprogramming completion signal.
 78. The device according to claim 67,wherein said applying, selective sensing and modifying are continueduntil each memory cell is sufficiently written.
 79. The device accordingto claim 67, wherein said write control voltages are simultaneouslyapplied to said respective of said memory cells.
 80. The deviceaccording to claim 79, wherein said write control voltages defined bysaid write control data stored in said data circuits and applied to saidrespective of said memory cells differ according to said write controldata stored in said data circuits.
 81. The device according to claim 67,wherein said data circuits are arranged adjacent to said memory cellarray.
 82. The device according to claim 67, wherein each of said datacircuits is connected to a respective one of said bit lines.
 83. Thedevice according to claim 67, wherein said data circuits include bitline voltage regulators for selectively changing voltages of said bitlines according to said write control data stored in said data circuits.84. The device according to claim 83, wherein said voltages of said bitlines are selectively and simultaneously changed by said bit linevoltage regulators.
 85. A multi-level non-volatile semiconductor memorydevice comprising: a semiconductor substrate; a plurality of bit lines;a plurality of word lines insulatively intersecting said bit lines; amemory cell array comprising a plurality of memory cells coupled to saidword lines or bit lines, each memory cell including a transistor with acharge storage portion and having written states of first, second, . . ., (n−1)th and nth (n≧3) predetermined storage levels; a plurality ofcell selection circuits coupled to said memory cell array forcontrolling selection of memory cells and application of write voltagesto the selected memory cells; a plurality of data circuits coupled tosaid memory cell array for storing write control data of first, second,. . . (n−1)th, and nth predetermined logic levels which define writecontrol voltages to be applied to respective of said memory cellsselected by said cell selection circuits, for applying said writecontrol voltages to said respective of said memory cells, for sensingactual written states of only those of said respective memory cellscorresponding to the data circuits in which the write control data ofsaid second, third, . . . , (n−1)th and nth predetermined logic levelsare stored, for modifying stored write control data from said ith (i=2,3, . . . , n−1, n) predetermined logic level to said first predeterminedlogic level to the data circuits storing the write control data of saidith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level andcorresponding to the memory cells in which successful writing of saidith (respectively, i=2, 3, . . . , n−1, n) predetermined storage levelhas been sensed, for maintaining said stored write control data at saidith (i=2, 3, . . . , n−1, n) predetermined logic level in the datacircuits storing the write control data of said ith (respectively, i=2,3, . . . , n−1, n) predetermined logic level and corresponding to thememory cells in which it has been sensed that said ith (respectively,i=2, 3, . . . , n−1, n) predetermined storage level has not beensuccessfully written, and for maintaining said stored write control dataat said first predetermined logic level in the data circuits storing thewrite control data of said first predetermined logic level; whereinresults of said sensing of said actual written states by the datacircuits storing the write control data of said ith (i=2, 3, . . . ,n−1, n) predetermined logic level are determined on the basis of onlywhether or not the written state of the respective memory cell is saidith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level.86. The device according to claim 85, wherein said write control datastored in said data circuits are initially set to initial write controldata, and then said initial write control data stored in said datacircuits are modified.
 87. The device according to claim 85, whereinsaid initial write control data are loaded from at least one input linecoupled to said data circuits.
 88. The device according to claim 85,wherein said actual written states of said memory cells corresponding tothe data circuits storing the write control data of said ith (i=2, 3, .. . , n−1, n) predetermined logic level are simultaneously sensed. 89.The device according to claim 85, wherein said actual written states ofsaid memory cells corresponding to the data circuits storing the writecontrol data of said second, third, . . . , (n−1)th and nthpredetermined logic levels are simultaneously sensed.
 90. The deviceaccording to claim 85, wherein said write control data of said ith (i=2,3, . . . , n−1, n) predetermined logic level stored in the data circuitscorresponding to the memory cells in which successful writing has beensensed are simultaneously modified to the write control data of saidfirst predetermined logic level.
 91. The device according to claim 85,wherein said write control data of said second, third, . . . , (n−1)thand nth predetermined logic levels stored in the data circuitscorresponding to the memory cells in which successful writing has beensensed are simultaneously modified to the write control data of saidfirst predetermined logic level.
 92. The device according to claim 85,further comprising a plurality of data write end detection circuitscoupled to said data circuits for simultaneously detecting whether ornot all of said data circuits store the write control data of said firstpredetermined logic level.
 93. The device according to claim 92, whereineach of said data write end detection circuits is provided for each ofsaid data circuits.
 94. The device according to claim 93, wherein saiddata write end detection circuits are coupled to at least one commonoutput line, and said data write end detection circuits output aprogramming completion signal on said common output line when each datacircuit stores the write control data of said first predetermined logiclevel.
 95. The device according to claim 94, wherein said applying,sensing and modifying are continued until said data write end detectioncircuits output said programming completion signal.
 96. The deviceaccording to claim 85, wherein said applying, sensing and modifying arecontinued until each memory cell is sufficiently written.
 97. The deviceaccording to claim 85, wherein said write control voltages aresimultaneously applied to said respective of said memory cells.
 98. Thedevice according to claim 97, wherein said write control voltagesdefined by said write control data stored in said data circuits andapplied to said respective of said memory cells differ according to saidwrite control data stored in said data circuits.
 99. The deviceaccording to claim 85, wherein said data circuits are arranged adjacentto said memory cell array.
 100. The device according to claim 85,wherein each of said data circuits is connected to a respective one ofsaid bit lines.
 101. The device according to claim 85, wherein said datacircuits include bit line voltage regulators for selectively changingvoltages of said bit lines according to said write control data storedin said data circuits.
 102. The device according to claim 101, whereinsaid voltages of said bit lines are selectively and simultaneouslychanged by said bit line voltage regulators.
 103. The device accordingto claim 85, wherein each of said results is stored in the respectivedata circuit and used as latest write control data.
 104. A multi-levelsemiconductor memory device comprising: a semiconductor substrate; aplurality of bit lines; a plurality of word lines insulativelyintersecting said bit lines; a memory cell array comprising a pluralityof memory cells coupled to said word lines and bit lines, each memorycell including a transistor with a charge storage portion and havingwritten states of first, second, . . . , (n−1)th and nth (n≧3)predetermined storage levels; a plurality of cell selection circuitscoupled to said memory cell array for controlling selection of memorycells and application of write voltages to the selected memory cells; aplurality of data circuits coupled to said memory cell array for storingwrite control data of first, second, . . . , (n−1)th, and nthpredetermined logic levels which define write control voltages to beapplied to respective of said memory cells selected by said cellselection circuits, for applying said write control voltages to saidrespective of said memory cells, for sensing actual written states ofonly those of said respective memory cells corresponding to the datacircuits in which the write control data of said second, third, . . . ,(n−1)th and nth predetermined logic levels are stored, for modifyingstored write control data from said ith (i=2, 3, . . . , n−1, n)predetermined logic level to said first predetermined logic level in thedata circuits storing the write control data of said ith (respectively,i=2, 3, . . . , n−1, n) predetermined logic level and corresponding tothe memory cells in which successful writing of said ith (respectively,i=2, 3, . . . , n−1, n) predetermined storage level has been sensed, formaintaining said stored write control data at said ith (i=2, 3, . . . ,n−1, n) predetermined logic level in the data circuits storing the writecontrol data of said ith (respectively, i=2, 3, . . . , n−1, n)predetermined logic level and corresponding to the memory cells in whichit has been sensed that said ith (respectively, i=2, 3, . . . , n−1, n)predetermined storage level has not been successfully written, and formaintaining said stored write control data at said first predeterminedlogic level in the data circuits storing the write control data of saidfirst predetermined logic level, wherein with respect to said sensing ofsaid actual written states, the data circuits storing the write controldata of said ith (i=2, 3, . . . , n−1, n) predetermined logic levelsense only whether or not the written state of the respective memorycell is said ith (respectively, i=2, 3, n−1, n) predetermined storagelevel.
 105. The device according to claim 104, wherein said writecontrol data stored in said data circuits are initially set to initialwrite control data, and then said initial write control data stored insaid data circuits are modified.
 106. The device according to claim 105,wherein said initial write control data are loaded from at least oneinput line coupled to said data circuits.
 107. The device according toclaim 104, wherein each of said data circuits is connected to arespective one of said bit lines, and the data circuits storing thewrite control data of said ith (i=2, 3, . . . , n−1, n) predeterminedlogic level sense voltage levels of the respective bit lines bycomparing with ith (respectively, i=2, 3, . . . , n−1, n) referencevoltage.
 108. The device according to claim 104, wherein said actualwritten states of said memory cells corresponding to the data circuitsstoring the write control data of said ith (i=2, 3, . . . , n−1, n)predetermined logic level are simultaneously sensed.
 109. The deviceaccording to claim 104, wherein said actual written states of saidmemory cells corresponding to the data circuits storing the writecontrol data of said second, third, . . . , (n−1)th and nthpredetermined logic levels are simultaneously sensed.
 110. The deviceaccording to claim 104, wherein said write control data of said ith(i=2, 3, . . . , n−1, n) predetermined logic level stored in the datacircuits corresponding to the memory cells in which successful writinghas been sensed are simultaneously modified to the write control data ofsaid first predetermined logic level.
 111. The device according to claim104, wherein said write control data of said second, third, . . . ,(n−1)th and nth predetermined logic levels stored in the data circuitscorresponding to the memory cells in which successful writing has beensensed are simultaneously modified to the write control data of saidfirst predetermined logic level.
 112. The device according to claim 104,wherein said applying, sensing and modifying are continued until eachmemory cell is sufficiently written.
 113. The device according to claim104, wherein said write control voltages are simultaneously applied tosaid respective of said memory cells.
 114. The device according to claim113, wherein said write control voltages defined by said write controldata stored in said data circuits and applied to said respective of saidmemory cells differ according to said write control data stored in saiddata circuits.
 115. The device according to claim 104, wherein said datacircuits are arranged adjacent to said memory cell array.
 116. Thedevice according to claim 104, wherein each of said data circuits isconnected to a respective one of said bit lines.
 117. The deviceaccording to claim 104, wherein said data circuits include bit linevoltage regulators for selectively changing voltages of said bit linesaccording to said write control data stored in said data circuits. 118.The device according to claim 117, wherein said voltages of said bitlines are selectively and simultaneously changed by said bit linevoltage regulators.
 119. The device according to claim 104, wherein eachof results of said sensing is stored in the respective data circuit andused as latest write control data.
 120. A multi-level non-volatilesemiconductor memory device comprising: a plurality of memory cells,each being capable of having one of first, second, and third storagelevels; and a plurality of programming control circuits coupled to eachof the memory cells, wherein each of said programming control circuitsis capable of storing in a data storage portion data of one of first,second, and third logic levels which define write voltage to be appliedto a corresponding memory cell, for applying said write voltage to thecorresponding memory cell according to the data stored in the datastorage portion, for determining whether the corresponding memory cellhas reached the second storage level only in case that the data storedin the data storage portion represents the second logic level, fordetermining whether the corresponding memory cell has reached the thirdstorage level only in case that the data stored in the data storageportion represents the third logic level, for modifying the stored datafrom the second logic level to the first logic level if it has beendetermined that the corresponding memory cell has reached the secondstorage level, for modifying the stored data from the third logic levelto the first logic level if it has been determined that thecorresponding memory cell has reached the third storage level, and formaintaining the stored data at the first logic level if the data storageportion has stored the data of the first logic level.
 121. The deviceaccording to claim 120, wherein the programming control circuits storingthe data of the first logic level apply a first write voltage, whichinhibits changes in the storage levels, to the corresponding memorycells.
 122. The device according to claim 121, wherein the programmingcontrol circuits storing the data of the second logic level apply asecond write voltage, which promotes changes to the second storage levelin the corresponding memory cells, to the corresponding memory cells,and the programming control circuits storing the data of the third logiclevel apply a third write voltage, which promotes changes to the thirdstorage level in the corresponding memory cells, to the correspondingmemory cells.
 123. The device according to claim 122 wherein said secondwrite voltage is different from said third write voltage.
 124. Thedevice according to claim 120, wherein each data storage portionincludes two CMOS flip-flop circuits.
 125. The device according to claim120, further comprising data detectors for detecting whether all of saiddata storage portions have stored the data of the first logic level.126. The device according to claim 120, wherein plural of the memorycells store-three bit data.